AS7C3512K18P Search Results

Contextual Info: Advance information •■ AS7C3512K16P AS7C3512K18P Il II 3.3V 512K- 16 ‘18 pipeline burst synchronous SRAM Features • • • • • • • • • Organization: 5 2 4 ,2 8 8 w ord s x 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access: 3 . 5 / 3 . 8 / 4 / 5 ns

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Abstract: nas77 3512K
Contextual Info: Features • • • • • • • • • Organization: 5 2 4 ,2 8 8 w ords x 16 or 18 bits Fast clock speeds to 166 MHz in LVTTL/LVCMOS Fast clock to data access'. 3 . 5 / 3 . 8 / 4 / 5 ns Fast UE access time: 3 . 5 / 3 . 5 / 3 . 8 / 4 ns Fully synchronous register-to-register operation

Contextual Info: Advance information •■ I l AS7C3512K16Z AS7C3512K18Z A 3.3V 5 1 2K x 1 6 /1 8 synchronous burst SRAM with ZBT1 Features • • • • • • • • • • • • • • • • • • • Organization: 524,288 words x 16 or 18 bits ZBT architecture for efficient bus operation

AIA4M

Abstract: VW99
Contextual Info: Advance informatio AS7C3512K16Z AS7C3512K18Z •3V 5 1 2 K x l 6 / 1 8 synchronous burst SRAM with ZBT Features • • • • • • • • • • ZZ sleep mode for lower power Byte write enables Single R/ W control pin Gock enable for operation hold

A301D

Abstract: A211D 4bc 82
Contextual Info: $GYDQFHLQIRUPDWLRQ $6&.3 $6&.3 9.ðSLSHOLQHEXUVWV\QFKURQRXV65$0  HDWXUHV • Multiple packaging options - Economical 100-pin TQFP package - Chip-scale fBGA package for smallest footprint • Byte write enables • Clock enable for operation hold

Contextual Info: $GYDQFHLQIRUPDWLRQ $6&.= $6&.= 9.ðV\QFKURQRXVEXUVW65$0ZLWK=%7Š HDWXUHV • ZZ sleep mode for lower power • Byte write enables • Single R/W control pin • Clock enable for operation hold • Multiple chip enables for easy expansion

L8150

Contextual Info: Features • • • • • • • • • • • ZZ sleep m ode for lower power • Byte write enables • Single R /W control pin • Clock enable for operation hold • Multiple chip enables for easy expansion •3 .3 V ± 5 % core power supply • 2.5V or 3.3V I/O operation with separate Vppg