ARCHITECTURE OF DUAL CORE Search Results

BGA180

Contextual Info: NXP 150 MHz, 32-bit Cortex-M4 /Cortex-M0 DSC LPC4300 series First asymmetrical, dual-core digital signal controller featuring Cortex-M4 & Cortex-M0 A dual-core architecture and a unique set of configurable peripherals make it possible to develop DSP and MCU applications within a single architecture and development environment.

Contextual Info: NXP 204 MHz, 32-bit Cortex-M4 /Cortex-M0 DSC LPC4300 series First asymmetrical, dual-core digital signal controller featuring Cortex-M4 & Cortex-M0 A dual-core architecture and a unique set of configurable peripherals make it possible to develop DSP and MCU applications within a single architecture and development environment.

Contextual Info: NXP 180 MHz, 32-bit Cortex-M4 /Cortex-M0 DSC LPC4300 series First asymmetrical, dual-core digital signal controller featuring Cortex-M4 & Cortex-M0 A dual-core architecture and a unique set of configurable peripherals make it possible to develop DSP and MCU applications within a single architecture and development environment.

60x-bus

Abstract: AN2335 PowerPC 60X Bus Interface controller MPC107 MPC8260 bus arbiter
Contextual Info: Freescale Semiconductor, Inc. Application Note AN2335/D Rev. 0, 10/2002 Freescale Semiconductor, Inc. MPC8260 Dual-Bus Architecture and Performance Considerations Eric Bost, NCSG Field Applications, France Paul Wilson, NCSD Applications, Scotland This document describes the dual-bus architecture of the MPC8260 PowerQUICC II and

voip ethernet single chip

Abstract: voip processor voip two ethernet free applications of arm7 processor voip codec chip tdmi features of ARM7 processor arm7 processor VOIP phone schematic STE100P
Contextual Info: VolP Processor Powers Cost Effective IP Telephony StradivariusTM integrates dual-core architecture, dual MAC Allowing voice and data to travel simultaneously over a single network, Voice-over-Internet-Protocol VoIP cuts the cost of voice telephony and enables new

voip codec chip

Abstract: voip ethernet single chip voip two ethernet voip processor VOIP phone schematic Voice Activity Detector D950 RFC2833 STE100P STLC1502
Contextual Info: VolP Processor for cost-effective IP telephony Stradivarius integrates dual-core architecture and dual MAC Allowing voice and data to travel simultaneously over a single network, Voice-over-Internet-Protocol VoIP cuts the cost of voice telephony and enables

AME5251

Abstract: GTSD32
Contextual Info: AME Dual 1A, 1.5MHz Synchronous Step-Down Converter AME5251 n General Description n Features The AME5251 is a high efficiency monolithic synchronous dual buck regulator using a constant frequency, current mode architecture. Capable of delivering 1A output

AME5251A

Contextual Info: AME Dual 1A, 1.5MHz Synchronous Step-Down Converter AME5251A n General Description n Features The AME5251A is a high efficiency monolithic synchronous dual buck regulator using a constant frequency, current mode architecture. Capable of delivering 1A output

TQFP52

Abstract: TQFP80
Contextual Info: µPSD323X Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY • The µPSD323X Devices combine a Flash PSD architecture with an 8032 microcontroller core. The µPSD323X Devices of Flash PSDs feature dual banks of Flash memory, SRAM, general

TQFP52

Abstract: TQFP80 t-con board
Contextual Info: µPSD325X Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY • The µPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The µPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM, general

upsd

Abstract: UPS3200 TQFP52 TQFP80 uPSD3200 uPSD3233B uPSD3233BV uPSD3234A uPSD3234A-40 uPSD3234BV
Contextual Info: uPSD3234A, uPSD3234BV uPSD3233B, uPSD3233BV Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY • The uPSD323X Devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD323X Devices of Flash PSDs feature dual banks of Flash memory, SRAM,

23TI

Abstract: UPS3200 TQFP52 TQFP80 uPSD3253B uPSD3253BV uPSD3254A uPSD3254BV uPSD325X BV-24
Contextual Info: uPSD3254A, uPSD3254BV uPSD3253B, uPSD3253BV Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY • The uPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM,

Contextual Info: µPSD325X Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM FEATURES SUMMARY • The µPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The µPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM, general

TQFP52

Abstract: TQFP80 uPSD3212C-40T6 uPSD3212C-40U6 uPSD3212CV-24T6 uPSD3212CV-24U6 uPSD321x
Contextual Info: µPSD321X Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM FEATURES SUMMARY • The µPSD321X Devices combine a Flash PSD architecture with an 8032 microcontroller core. The µPSD321X Devices of Flash PSDs feature dual banks of Flash memory, SRAM, general

mod 8 ring counter using JK flip flop

Abstract: AI07802 programmable multi pulse waveform generator cpld uPSD TQFP52 TQFP80 220 resistor array
Contextual Info: µPSD325X Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM FEATURES SUMMARY • The µPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The µPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM, general

dlna Schematic

Abstract: NAS 7825 hd DVR soc 862-NAS7825-AABCF
Contextual Info: NAS 7825, Next Generation Multi-functional Networked Storage Solution Key Benefits The Evolution of the Consumer Market Unique Trident architecture including dual-core ARM 11 MP each core running at 750 MHz, application specific hardware engines for networking, storage,

MPC5668G

Abstract: sram ecc Tresos e200z6 IC3000 Lauterbach nexus car gateway architecture wiggler NEXUS TRACE32
Contextual Info: MCU Built on Power Architecture Technology Qorivva MPC5668G Single-Chip Automotive Gateway Dual-core MCU with on-chip FlexRay , Ethernet and media local bus Overview Electronic content in vehicles keeps increasing. A number of different communication protocols,

P2020EC

Contextual Info: Freescale Semiconductor Data Sheet: Technical Data Document Number: P2020EC Rev. 2, 08/2013 P2020 P2020 QorIQ Integrated Processor Hardware Specifications The following list provides an overview of the P2020 feature set: • Dual high-performance Power Architecture e500 cores.

ba6l

Abstract: BA5L BA4L
Contextual Info: HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 2K x 36 banks – 4 megabits of memory on chip

LED 5630

Abstract: 5630 LED A101L 5630
Contextual Info: HIGH-SPEED 3.3V 128K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V7399S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 18 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 2K x 18 banks – 2 megabits of memory on chip

PF09

Abstract: HMVIP standard L16 eeprom SRAM-16K ADSP-BF561 DMAC ADSP-BF561SKBZ k08 transistor fet B20 p03 BC2561
Contextual Info: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory see Memory Architecture on Page 4 Each Blackfin core includes Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

Contextual Info: C8051F912-GDI Tested Single/Dual Battery, 0.9–3.6 V, 16 kB Flash, SmaRTClock, 12/10-Bit ADC MCU Die in Wafer Form High-Speed 8051 C Core - Pipelined instruction architecture; executes 70% of Ultra-Low Power - 160 µA/MHz in active mode 24.5 MHz clock

"64-Bit Microprocessor"

Abstract: IEEE1284 RC32364 RC5000
Contextual Info: RISCore64600 Product Brief RISCore64600TM Advanced Generation 64-bit Microprocessor Featur tures List ◆ ◆ Advanced architecture 64-bit Microprocessor – Super- pipelined to enable high frequency operation – Out of order dual issue to multiple functional units

tdc 310

Abstract: ba6l BA6R 10 35L U1
Contextual Info: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip