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TC4086BP

Contextual Info: TC4086BP TC40B6BP C 2MOS D IG IT A L IN T E G R A T E D CIRC UIT S ILIC O N M O N O LIT H IC EXPANDABLE 4-WIDE 2-INPUT AND-OR-INVERT GATE TC4086BP contains four 2 input AND gates and one OR gate which logically adds OR all the ANDgates having an expander input to form AND-OR-select gate,

plhs18p8

Abstract: PLHS18 PLHS18P8A
Contextual Info: Signetics Military Standard Products PLHS18P8A Programmable AND Array Logic 18x72x8 Product Specification PIN CONFIGURATION DESCRIPTION FE A TU R E S The PLHS18P8A is a two-level logic ele­ ment consisting of 72 ANDgates and SOR gates with fusible connections for pro­

DD 127 D TRANSISTOR

Contextual Info: rZ 7 S G S -T H O M S O N Ë [RfflD g[E [l[LI Tri®K]D©i HCC/HCF4068B 8-INPUT NAND/ANDGATE . MEDIUM-SPEED OPERATION - tpHL tpm = 75ns (typ. AT 10V • BUFFERED OUTPUT . QUIESCENT CURRENT SPECIHED TO 20V FOR HCC DEVICE . 5V, 10V, AND 15V PARAMETRIC RATINGS

MH 7472

Abstract: ic 7472 ttl 7472 ttl TTL 7472
Contextual Info: SN5472, SN7472 AND-GATED J-K M ASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1963 - REVISED MARCH 1988 S N 5 4 7 2 . . J P AC KA G E S N 7 4 7 2 . . . N P AC K A G E Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages TO P VIE W

rneg2

Contextual Info: QT1F-Plus Device Quad T1 Framer-Plus TXC-03103C DESCRIPTION • D4 SF, ESF including HDLC Link support , and transparent framing modes • Encodes/decodes AMI/B8ZS and forced ones density line codes • Fractional T1 gapped clock • Monitor function for frame pulse, clock and data

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

A115-A

Abstract: C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403D – APRIL 1998 – REVISED JANUARY 2001 D D D D SN54LV164A . . . J OR W PACKAGE SN74LV164A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115D – DECEMBER 1982 – REVISED AUGUST 2003 D D D D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 20 ns

SN54L71

Contextual Info: TYPESN54L71 AND-GATED R-S MASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR ' D e p e n d a b le T exas In s tru m e n ts Q u a lity and R e lia b ility REVISED DECEMBER 1983 S N 5 4 L 7 1 . . . J P AC K A G E {TO P V IE W NCC 1 CLRC 2 S1C 3 S2C 4 Ü 1 4 D vcc

LV164A

Abstract: A115-A C101 SN54LV164A SN74LV164A
Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403G − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF

integrated circuit sn74hc164n diagram

Abstract: SN74HC164N
Contextual Info: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115C – DECEMBER 1982 – REVISED DECEMBER 2002 D D D D D D D D D SN54HC164 . . . J OR W PACKAGE SN74HC164 . . . D, N, NS, OR PW PACKAGE TOP VIEW Wide Operating Voltage Range of 2 V to 6 V

set top box video recorder

Contextual Info: TSB42AA4/42AA4I TSB42AB4/42AB4I ceLynx IEEE 1394.a Consumer Electronics Link Layer Controller Data Manual April 2003 Mixed Signal Products SLLS341E IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

TMS320C5000

Abstract: XDS100 TMS320C5514
Contextual Info: TMS320C5514 SPRS646D – AUGUST 2010 – REVISED APRIL 2011 www.ti.com TMS320C5514 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5514 1 Fixed-Point Digital Signal Processor 1.1 Features 12 • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor

PAL16H8

Abstract: 16H8 8103614RX AmPAL16
Contextual Info: AmPAL*16XX Family 20-Pin IMOX Programmable Array Logic PAL Elements PRELOAD feature permits full logical verification Reliability assured through more than 70 billion fuse hours of life testing with no failures Full AC and DC parametric testing at the factory through

Contextual Info: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115E − DECEMBER 1982 − REVISED NOVEMBER 2010 D D D D D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80- A Max ICC Typical tpd = 20 ns

Contextual Info: TMS320C5515 SPRS645D – AUGUST 2010 – REVISED APRIL 2011 www.ti.com TMS320C5515 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5515 1 Fixed-Point Digital Signal Processor 1.1 Features 12 • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor

SN7470

Contextual Info: SN5470, SN7470 AND-GATED J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR SDLS116 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN54LV164A, SN74LV164A 8ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 14 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE

Contextual Info: SN54LV164A, SN74LV164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS403H − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 10.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 5 11 10 9 6 8 7 VCC QH QG QF QE CLR CLK

SN74HC104

Abstract: 54HC164
Contextual Info: SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SH IR REGISTERS SCLS115A - DECEM BER 1982 - REVISED JANUARY 1996 AND-Gated Enable/Disable Serial Inputs • • SN54HC164 . . . J OR W PACKAGE SN74HC164 . . . D OR N PACKAGE (TOP VIEW) Fully Buffered Clock and Serial Inputs

Contextual Info: 8-BIT SN74ALS164 PARALLEL-OUT SERIAL SHIFT REGISTERS D2M1. APRIL 1982 - REVISED JANUARY 1989 AND-Gated Enable/Citable Serial Input* S N 7 4 A L 8 W 4 . . . D OR N PACKAGE (TO P V IE W ) Fully Buffered Clock and Serial Input* Direct Clear Package Option* Include Plaatlc "Smalt

16H8

Abstract: AMD 16L8 AMPAL16H8 16a8 AmPAL16R6 AMPAL16L8/BRA AmPAL16R8 16LD8 TFK S 417 T pAL programming Guide
Contextual Info: AmPAL*16XX Family 20-Pin IMOX Programmable Array Logic PAL Elements PRELOAD feature perm its full logical verification Reliability assured through m ore than 70 billion fuse hours o f life testing w ith no failures Full AC and DC param etric testing at the factory through

SN7472

Abstract: SN54110 SN74 SN74110
Contextual Info: TYPES SN54110, SN74110 AND-GATED J -K MASTER-SLAVE FLIP-FLOPS WITH DATA LOCKOUT REVISED DECEMBER 1983 P a cka g e O p tio n s In c lu d e P la s tic and C e ra m ic DIPs S N 5 4 1 10 . . . J OR W PACKAG E S N 7 4 1 10 . . . J O R N PACKAGE T O P V IE W

Contextual Info: TMS320C5515 www.ti.com SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013 TMS320C5515 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5515 1 Fixed-Point Digital Signal Processor 1.1 Features 12 • High-Performance, Low-Power, TMS320C55x Fixed-Point Digital Signal Processor