AND8002 2012 B Search Results

On semiconductor date Code

Abstract: motorola MARKING CODE SO-8 MOTOROLA LOT MARKINGS BRD8011/D marking code motorola ic Date Code Formats motorola traceability code 2012 Identification Traceability marking code onsemi Diode date sheet of ba for the year 2011
Contextual Info: AND8002/D ECLinPS , ECLinPS Lite™, ECLinPS Plus™, ECLinPS MAX™, and GigaComm™ Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and

MOTOROLA LOT MARKINGS

Abstract: On semiconductor date Code IC Lot Code Identification marking code 6L QFN tray qfn 4x4 AND8002 ase qfn unisem QFN marking code onsemi Diode on alpha year and work week
Contextual Info: AND8002/D Clock Generation and Clock and Data Marking and Ordering Information Guide http://onsemi.com Prepared by: Paul Shockman ON Semiconductor APPLICATION NOTE Introduction This application note describes the device markings and ordering information for the following ON Semiconductor

On semiconductor date Code

Abstract: AND8002 AA MARKING CODE SO8 on alpha year and work week date code for semiconductor MOTOROLA LOT MARKINGS On semiconductor LQFP-52 motorola MARKING CODE SO-8 ON Semiconductor marking code
Contextual Info: AND8002/D ECLinPS , ECLinPS Lite™, ECLinPS Plus™, ECLinPS MAX™, and GigaComm™ Marking and Ordering Information Guide http://onsemi.com APPLICATION NOTE Prepared by: Paul Shockman ON Semiconductor HFPD Applications Engineer Introduction This application note describes the device markings and

KPT22

Contextual Info: MC100EPT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8−lead

MC100EPT21DG

Contextual Info: MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL , LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small

Contextual Info: MC100LVE210 3.3V ECL Dual 1:4, 1:5 Differential Fanout Buffer Description The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device

488AM

Abstract: lqfp-32 footprint layout
Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

10H351

Contextual Info: MC10H351 Quad TTL/NMOS to PECL* Translator Description The MC10H351 is a quad translator for interfacing data between a saturated logic section and the PECL section of digital systems when only a +5.0 Vdc power supply is available. The MC10H351 has TTL/NMOS compatible inputs and PECL complementary

k 790

Contextual Info: MC10H352 Quad CMOS to PECL* Translator Description The MC10H352 is a quad translator for interfacing data between a CMOS logic section and the PECL section of digital systems when only a +5.0 Vdc power supply is available. The MC10H352 has CMOS compatible inputs and PECL complementary open−emitter

Contextual Info: MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

lqfp-32 footprint layout

Abstract: MC100LVEP111MNG MC100LVEP111 AN1568 MC100LVEP111FARG M100LVEP111FATW M100LVEP111FATWG MC100LVEP111MNRG MC100LVEP111FAG
Contextual Info: MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or

KR22

Contextual Info: MC100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description Features • • • • • • • 350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation

MC100LVEP111

Contextual Info: MC100LVEP111 2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or

10H350G

Abstract: MC10H350
Contextual Info: MC10H350 PECL* to TTL Translator +5 Vdc Power Supply Only Description The MC10H350 is a member of the 10H family of high performance ECL logic. It consists of 4 translators with differential inputs and TTL outputs. The 3−state outputs can be disabled by applying a HIGH TTL

3n551

Abstract: 3n55 NB3N551DG
Contextual Info: NB3N551 3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer Description The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed for clock distribution in mind. The NB3N551 specifically guarantees low output−to−output skew. Optimal design, layout and processing

Contextual Info: NB3N551 3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer Description The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed for clock distribution in mind. The NB3N551 specifically guarantees low output−to−output skew. Optimal design, layout and processing

Contextual Info: NB3N106K 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The NB3N106K is a differential 1:6 Clock fanout buffer with High−speed Current Steering Logic HCSL outputs optimized for ultra low propagation delay variation. The NB3N106K is designed

Contextual Info: NB3L14S 2.5 V 1:4 LVDS Fanout Buffer The NB3L14S is a differential 1:4 LVDS Clock fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. The NB3L14S LVDS signals will be buffered and replicated to identical LVDS copies of the Input

Contextual Info: NB3L553 2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer Description The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for clock distribution in mind. The NB3L553 specifically guarantees low output−to−output skew. Optimal design, layout and processing

Contextual Info: NB3N106K 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The NB3N106K is a differential 1:6 Clock fanout buffer with High−speed Current Steering Logic HCSL outputs optimized for ultra low propagation delay variation. The NB3N106K is designed

Contextual Info: NB3L553 2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer Description The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for clock distribution in mind. The NB3L553 specifically guarantees low output−to−output skew. Optimal design, layout and processing

AND8002 2012 B

Contextual Info: MC100LVEL34 3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip Description The MC100LVEL34 is a low skew ÷ 2, ÷ 4, ÷ 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the

Contextual Info: NB3L83948C 2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX to 1:12 LVCMOS Fanout Description The NB3L83948C is a pure 2.5 V / 3.3 V VDD = VDDO or mixed mode 3.3 V Core (VDD) / 2.5 V Output (VDDO) clock distribution buffer with the capability to select either a differential LVPECL /

Contextual Info: NB3N111K 3.3V Differential 1:10 Fanout Clock Driver with HCSL Outputs Description http://onsemi.com The NB3N111K is a differential 1:10 Clock fanout buffer with High−speed Current Steering Logic HCSL outputs optimized for ultra low propagation delay variation. The NB3N111K is designed