488AM Search Results

smd marking l1a

Abstract: NCN6804 L2B14 smd TRANSISTOR code b6 ISO7816 NCN6001 NCN6004A NCN6804MNR2G QFN32 QFN-32
Contextual Info: NCN6804 Dual Smart Card Interface IC with SPI Programming Interface http://onsemi.com MARKING DIAGRAM 1 QFN32 CASE 488AM A L Y W G Features •ăPoint Of Sales POS and Transaction Terminals •ăATM (Automatic Teller Machine) / Banking Terminal Interfaces

98AON20032D

Abstract: QFN32 488AM-01 488AM
Contextual Info: MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN32 5*5*1 0.5 P CASE 488AM−01 ISSUE O DATE 18 APR 2005 1 32 SCALE 2:1 A B ÉÉ ÉÉ D PIN ONE LOCATION 0.15 C 2X 2X NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS.

smd TRANSISTOR code b6

Abstract: ISO7816 NCN6001 NCN6004A NCN6804 NCN6804MNR2G QFN32 cms capacitor smd marking l1a K TRANSISTOR SMD MARKING CODE T12
Contextual Info: NCN6804 Dual Smart Card Interface IC with SPI Programming Interface http://onsemi.com MARKING DIAGRAM 1 QFN32 CASE 488AM A L Y W G Features • Point Of Sales POS and Transaction Terminals • ATM (Automatic Teller Machine) / Banking Terminal Interfaces

MC100EL91

Abstract: MC100EPT25 MC100LVEP16 MC10LVEP16 100H646
Contextual Info: AND8072/D Thermal Analysis and Reliability of WIRE BONDED ECL Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE WIRE BONDED Device Failure Mechanisms For the plastic DIP, SOIC, TSSOP, PLCC, TQFP, and

Contextual Info: NB4N840M 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination http://onsemi.com MARKING DIAGRAM Description The NB4N840M is a high−bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for

Contextual Info: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar

Contextual Info: MC100EP195B 3.3V ECL Programmable Delay Chip Descriptions The MC100EP195B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and

ADP3211 D

Abstract: ADP3211A ADP3211 ntc r54 ATOM snubber capacitor intel atom microprocessor NTMFS4821N NTMFS4846N NTMS4846N QFN32
Contextual Info: ADP3211, ADP3211A 7-Bit, Programmable, Single-Phase, Synchronous Buck Controller The ADP3211 is a highly efficient, single−phase, synchronous buck switching regulator controller. With its integrated driver, the ADP3211 is optimized for converting the notebook battery voltage to

QFN-32 footprint

Abstract: 32 pins qfn 5x5 footprint marking dj2 QFN-32 NB6VQ572MMNG PRBS23 QFN32 NB7V572M
Contextual Info: NB6VQ572M 1.8V / 2.5V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator http://onsemi.com Multi−Level Inputs w/ Internal Termination MARKING DIAGRAM Description The NB6VQ572M is a high performance differential 4:1 Clock / Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that

Contextual Info: A5191HRT HART Modem Description The A5191HRT is a single−chip, CMOS modem for use in highway addressable remote transducer HART field instruments and masters. The modem and a few external passive components provide all of the functions needed to satisfy HART physical layer requirements

a5 gnd

Abstract: a5 gnd 700
Contextual Info: NB3V8312C Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer The NB3V8312C is a high performance, low skew LVCMOS fanout buffer which can distribute 12 ultra−low jitter clocks from an LVCMOS/LVTTL input up to 250 MHz. The 12 LVCMOS output pins drive 50 W series or parallel

Contextual Info: NB3F8L3010C 3.3V / 2.5V / 1.8V / 1.5V 1:10 LVCMOS Fanout Buffer Description The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V / 1.5 V VDDOn supplies which must be equal or less than VDD.

Contextual Info: MC100EP210S 2.5V 1:5 Dual Differential LVDS Compatible Clock Driver Description The MC100EP210S is a low skew 1−to−5 dual differential driver, designed with LVDS clock distribution in mind. The LVDS or LVPECL input signals are differential and the signal is fanned out to

Contextual Info: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator Description The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR−ed enable input which

E131

Abstract: MC100EP131 MC10EP131 QFN32 QFN32* socket
Contextual Info: MC10EP131, MC100EP131 3.3V / 5V ECL Quad D Flip−Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables.

Contextual Info: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is

NCP5378MNR2G

Abstract: QFN32 VR11 IC DAC-08 00 QFN32 5X5 GND AA
Contextual Info: NCP5378 Single Phase Synchronous Buck Controller with Integrated Gate Drivers and Programmable DAC • • • • • • • • • • • • • • • • • • • • Meets Intel’s VR11.1 Specifications High Performance Operational Error Amplifier

NB4N111KMNG

Abstract: NB4N111KMNR4G QFN32 488AM
Contextual Info: NB4N111K 3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output http://onsemi.com Description The NB4N111K is a differential input clock 1 to 10 HCSL fanout buffer, optimized for ultra low propagation delay variation. The NB4N111K is designed with HCSL clock distribution for FBDIMM

ps2018

Contextual Info: NB4N840M 3.3V 2.7Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination http://onsemi.com MARKING DIAGRAM Description The NB4N840M is a high−bandwidth fully differential dual 2 x 2 crosspoint switch with CML inputs/outputs that is suitable for

Contextual Info: NB7L572 2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator http://onsemi.com Multi−Level Inputs w/ Internal Termination The NB7L572 is a high performance differential 4:1 Clock/Data input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer. The

Contextual Info: NB4L339 2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan−Out Buffer http://onsemi.com Multi−Level Inputs w/ Internal Termination Description The NB4L339 is a multi−function Clock generator featuring a 2:1

LQFP-32 footprint

Abstract: L-98 LQFP32 footprint
Contextual Info: MC10EP142, MC100EP142 3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in

lqfp-32 footprint layout

Abstract: LQFP-32 MC12429 MPC9229 NBC12429 NBC12429A PLCC-28 QFN32
Contextual Info: NBC12429, NBC12429A 3.3V/5V Programmable PLL Synthesized Clock Generator 25 MHz to 400 MHz http://onsemi.com Description The NBC12429 and NBC12429A are general purpose, Phase-Lock-Loop PLL based synthesized clock sources. The VCO will operate over a frequency range of 200 MHz to 400 MHz. The

VCF12

Abstract: LQFP-32 MC100 QFN32 QFN-32
Contextual Info: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar