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    AMBA AXI SPECIFICATIONS Search Results

    AMBA AXI SPECIFICATIONS Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    PEF24628EV1X
    		Rochester Electronics LLC PEF24628 - SOCRATES Four-channel SHDSL EFM system-on-chip PDF Buy
    HM1L52LDP242H2PLF
    		Amphenol Communications Solutions Right Angle Signal Header, 60 Position Press-Fit, Specific Loading PDF
    HM1L52LDP242H6PLF
    		Amphenol Communications Solutions Right Angle Signal Header, 60 Position Press-Fit, Specific Loading PDF
    SM28VLT32SKGD1
    		Texas Instruments 32-Mbit High-Temp Flash ASIC With Serial Peripheral Interface (SPI) Bus 0-XCEPT Visit Texas Instruments
    CDC341DWR
    		Texas Instruments 1-to-8 clock driver with tight AC specification 20-SOIC 0 to 70 Visit Texas Instruments Buy

    AMBA AXI SPECIFICATIONS Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    uart 16550

    Abstract: XC6SLX16CSG324 AMBA AXI4 XC6SLX16-CSG324 XC6VLX75T-FF784 uart vhdl fpga UART16550 V6 6D XC7V855T National Semiconductor PC16550D UART
    Contextual Info: LogiCORE IP AXI UART 16550 v1.01a DS748 June 22, 2011 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced


    Original     		DS748 PC16550D uart 16550 XC6SLX16CSG324 AMBA AXI4 XC6SLX16-CSG324 XC6VLX75T-FF784 uart vhdl fpga UART16550 V6 6D XC7V855T National Semiconductor PC16550D UART PDF

    XC6SLX16-CSG324

    Abstract: XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3
    Contextual Info: LogiCORE IP AXI UART 16550 v1.01a DS748 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced


    Original     		DS748 PC16550D PC165otify XC6SLX16-CSG324 XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3 PDF

    xc6s

    Abstract: XC7K410T tlr1
    Contextual Info: LogiCORE IP AXI Timer axi_timer (v1.03.a) DS764 July 25, 2012 Product Specification Introduction LogiCORE IP Facts This document describes the specifications for a Advanced Microcontroller Bus Architecture (AMBA ) specification’s Advanced eXtensible Interface (AXI)


    Original     		DS764 32/64-bit ZynqTM-7000 xc6s XC7K410T tlr1 PDF

    XC6SL

    Abstract: XC7K410T axi master PLBv46 slave DS711
    Contextual Info: n LogiCORE IP PLBV46 to AXI Bridge v2.01.a DS711 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Processor Local Bus (PLB v4.6) to Advanced Microcontroller Bus Architecture (AMBA ) Advanced eXtensible Interface (AXI) Bridge translates PLBV46


    Original     		PLBV46 DS711 ZynqTM-7000 PLBV46, XC6SL XC7K410T axi master PLBv46 slave PDF

    g17g2

    Abstract: state machine axi 3 protocol state machine diagram for axi bridge state machine axi DS712 G17G-2 AMBA AXI specifications 17256 XILINX
    Contextual Info: LogiCORE IP AXI PLBv46 Bridge v2.02.a DS712 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced Microcontroller Bus Architecture (AMBA ) Advanced eXtensible Interface (AXI4) to Processor Local Bus (PLB v4.6) Bridge translates AXI


    Original     		PLBv46 DS712 32/64-bit ZynqTM-7000 g17g2 state machine axi 3 protocol state machine diagram for axi bridge state machine axi G17G-2 AMBA AXI specifications 17256 XILINX PDF

    XC6SLX

    Abstract: 2ffg1157 xps usb2 XC6SLX150
    Contextual Info: LogiCORE IP AXI Universal Serial Bus 2.0 Device v3.00a DS785 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Universal Serial Bus 2.0 High Speed Device with an AMBA® AXI interface enables USB connectivity to a design using a minimal amount of resources. This


    Original     		DS785 ZynqTM-7000, XC6SLX 2ffg1157 xps usb2 XC6SLX150 PDF

    axi ethernet lite software example

    Abstract: zynq axi ethernet software example microblaze ethernet V101A microblaze axi ethernet lite microblaze ethernet lite
    Contextual Info: LogiCORE IP Ethernet Lite MAC v1.01a DS787 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AMBA AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3


    Original     		DS787 axi ethernet lite software example zynq axi ethernet software example microblaze ethernet V101A microblaze axi ethernet lite microblaze ethernet lite PDF

    adr-301

    Abstract: NIC-301 AMBA Network Interconnect NIC-301 Implementation Guide AMBA AXI to AHB BUS Bridge verilog code state diagram of AMBA AXI protocol v 1.0 AMBA AXI designer user guide verilog rtl code of Crossbar Switch AMBA AHB bus protocol AMBA AXI verilog code nic301
    Contextual Info: CoreLink Network Interconnect NIC-301 Revision: r2p2 Technical Reference Manual Copyright 2006-2010 ARM. All rights reserved. ARM DDI 0397H ID080710 CoreLink Network Interconnect NIC-301 Technical Reference Manual Copyright © 2006-2010 ARM. All rights reserved.


    Original     		NIC-301 0397H ID080710) ID080710 32-bit adr-301 NIC-301 AMBA Network Interconnect NIC-301 Implementation Guide AMBA AXI to AHB BUS Bridge verilog code state diagram of AMBA AXI protocol v 1.0 AMBA AXI designer user guide verilog rtl code of Crossbar Switch AMBA AHB bus protocol AMBA AXI verilog code nic301 PDF

    AMBA AXI designer user guide

    Abstract: AMBA AXI dma controller designer user guide AMBA Network Interconnect NIC-301 Implementation Guide NIC-301 nic301 QoS-301 ARM DII 0222 adr-301 AMBA 3.0 technical reference manual dii 0157
    Contextual Info: AMBA Network Interconnect Advanced Quality of Service QoS-301 Revision: r0p0 Technical Reference Manual Copyright 2010 ARM. All rights reserved. ARM DDI 0451A (ID030610) AMBA Network Interconnect Advanced Quality of Service (QoS-301) Technical Reference Manual


    Original     		QoS-301) ID030610) 32-bit ID030610 AMBA AXI designer user guide AMBA AXI dma controller designer user guide AMBA Network Interconnect NIC-301 Implementation Guide NIC-301 nic301 QoS-301 ARM DII 0222 adr-301 AMBA 3.0 technical reference manual dii 0157 PDF

    AMBA AXI

    Abstract: JEP106 state diagram of AMBA AXI protocol v 1.0 timing diagram of AMBA apb protocol JEP-106 AMBA AXI to APB BUS Bridge transistor B1010 ADR-301 BP135 axi to apb bridge
    Contextual Info: TrustZone Address Space Controller TZC-380 Revision: r0p0 Technical Reference Manual Copyright 2008, 2010 ARM Limited. All rights reserved. ARM DDI 0431B (ID4/1/10) TrustZone Address Space Controller (TZC-380) Technical Reference Manual Copyright © 2008, 2010 ARM Limited. All rights reserved.


    Original     		TZC-380) 0431B ID4/1/10) ID040110 AMBA AXI JEP106 state diagram of AMBA AXI protocol v 1.0 timing diagram of AMBA apb protocol JEP-106 AMBA AXI to APB BUS Bridge transistor B1010 ADR-301 BP135 axi to apb bridge PDF

    axi to apb bridge

    Abstract: JEP106 secure ADR-301 trustzone TZC-380 JEP-106 AMBA AXI transistor B1010 AMBA AXI specifications
    Contextual Info: CoreLink TrustZone Address Space Controller TZC-380 Revision: r0p1 Technical Reference Manual Copyright 2008, 2010 ARM Limited. All rights reserved. ARM DDI 0431C ID090910 CoreLink TrustZone Address Space Controller TZC-380 Technical Reference Manual


    Original     		TZC-380 0431C ID090910) ID090910 axi to apb bridge JEP106 secure ADR-301 trustzone TZC-380 JEP-106 AMBA AXI transistor B1010 AMBA AXI specifications PDF

    FD001

    Abstract: AMBA AXI to APB BUS Bridge verilog code AMBA AXI designer user guide AMBA APB bus protocol axi crossbar AMBA axi to apb bridge PL301 AMBA AHB to APB BUS Bridge verilog code verilog rtl code of Crossbar Switch
    Contextual Info: PrimeCell High-Performance Matrix PL301 Revision: r1p0 Technical Summary Copyright 2006 ARM Limited. All rights reserved. ARM DDI 0422A PrimeCell High-Performance Matrix (PL301) Technical Summary Copyright © 2006 ARM Limited. All rights reserved.


    Original     		PL301) 32-bit FD001 AMBA AXI to APB BUS Bridge verilog code AMBA AXI designer user guide AMBA APB bus protocol axi crossbar AMBA axi to apb bridge PL301 AMBA AHB to APB BUS Bridge verilog code verilog rtl code of Crossbar Switch PDF

    lpddr2

    Abstract: micron lpddr2 lpddr2 datasheet micron lpddr2 datasheet Datasheet LPDDR2 SDRAM Jedec JESD209 lpddr2 phy lpddr JESD209-2 LPDDR2 SDRAM memory
    Contextual Info: AMBA LPDDR2 Dynamic Memory Controller DMC-342 Revision: r0p0 Technical Reference Manual Copyright 2009 ARM. All rights reserved. ARM DDI 0436A ID103109 AMBA LPDDR2 Dynamic Memory Controller DMC-342 Technical Reference Manual Copyright © 2009 ARM. All rights reserved.


    Original     		DMC-342 ID103109) 32-bit ID103109 lpddr2 micron lpddr2 lpddr2 datasheet micron lpddr2 datasheet Datasheet LPDDR2 SDRAM Jedec JESD209 lpddr2 phy lpddr JESD209-2 LPDDR2 SDRAM memory PDF

    Jedec JESD209

    Abstract: DMC TOOL AMBA AXI dma controller designer user guide DMC-340 PL301 ADR-301 ddr phy trustzone DMC-340 Supplement to AMBA Designer arlen
    Contextual Info: AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Revision: r4p0 Technical Reference Manual Copyright 2004-2007, 2009 ARM Limited. All rights reserved. ARM DDI 0331G ID111809 AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference Manual


    Original     		DMC-340 0331G ID111809) 32-bit ID111809 Jedec JESD209 DMC TOOL AMBA AXI dma controller designer user guide DMC-340 PL301 ADR-301 ddr phy trustzone DMC-340 Supplement to AMBA Designer arlen PDF

    FD001

    Abstract: state diagram of AMBA AXI protocol v 1.0 AMBA file write AXI verilog code AMBA AXI ddr phy interface AMBA AXI designer user guide AMBA AXI to APB BUS Bridge verilog code PL341 AMBA AXI dma controller designer user guide FD001 User Guide ARM DUI 0333
    Contextual Info: PrimeCell DDR2 Dynamic Memory Controller PL341 Revision: r1p0 Technical Reference Manual Copyright 2007, 2009 ARM Limited. All rights reserved. ARM DDI 0418D (ID050909) PrimeCell DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual Copyright © 2007, 2009 ARM Limited. All rights reserved.


    Original     		PL341) 0418D ID050909) ID041709 32-bit FD001 state diagram of AMBA AXI protocol v 1.0 AMBA file write AXI verilog code AMBA AXI ddr phy interface AMBA AXI designer user guide AMBA AXI to APB BUS Bridge verilog code PL341 AMBA AXI dma controller designer user guide FD001 User Guide ARM DUI 0333 PDF

    DMA Controller DMA-330 Supplement to AMBA Designer ADR-301 User Guide

    Abstract: adr-301 DMA-330 AMBA AXI dma controller designer user guide armv7-a dma 330 user guide pl330 DMA Controller PL330 Technical Reference Manual state machine for axi to apb bridge pl330 dma AMBA AXI
    Contextual Info: CoreLink DMA Controller DMA-330 Revision: r1p1 Technical Reference Manual Copyright 2007, 2009-2010 ARM Limited. All rights reserved. ARM DDI 0424C ID080710 CoreLink DMA Controller DMA-330 Technical Reference Manual Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.


    Original     		DMA-330 0424C ID080710) 32-bit ID080710 DMA Controller DMA-330 Supplement to AMBA Designer ADR-301 User Guide adr-301 DMA-330 AMBA AXI dma controller designer user guide armv7-a dma 330 user guide pl330 DMA Controller PL330 Technical Reference Manual state machine for axi to apb bridge pl330 dma AMBA AXI PDF

    AMBA AXI verilog code

    Abstract: AMBA AXI to APB BUS Bridge verilog code state diagram of AMBA AXI protocol v 1.0 FD001 User Guide ARM DUI 0333 PL341 FD001 AMBA AXI specifications 0418C ARM DUI 0333
    Contextual Info: PrimeCell DDR2 Dynamic Memory Controller PL341 Revision: r0p1 Technical Reference Manual Copyright 2007 ARM Limited. All rights reserved. ARM DDI 0418C PrimeCell DDR2 Dynamic Memory Controller (PL341) Technical Reference Manual Copyright © 2007 ARM Limited. All rights reserved.


    Original     		PL341) 0418C 32-bit AMBA AXI verilog code AMBA AXI to APB BUS Bridge verilog code state diagram of AMBA AXI protocol v 1.0 FD001 User Guide ARM DUI 0333 PL341 FD001 AMBA AXI specifications 0418C ARM DUI 0333 PDF

    Dynamic Memory Controller

    Abstract: AMBA AXI dma controller designer user guide verilog code for amba apb master PL340 edram macro AMBA AHB to APB BUS Bridge verilog code AMBA AXI designer user guide AMBA AXI to APB BUS Bridge verilog code FD001 User Guide ARM DUI 0333 0x00000212
    Contextual Info: PrimeCell Dynamic Memory Controller PL340 Revision: r2p0 Technical Reference Manual Copyright 2004-2007 ARM Limited. All rights reserved. ARM DDI 0331E PrimeCell Dynamic Memory Controller (PL340) Technical Reference Manual Copyright © 2004-2007 ARM Limited. All rights reserved.


    Original     		PL340) 0331E Dynamic Memory Controller AMBA AXI dma controller designer user guide verilog code for amba apb master PL340 edram macro AMBA AHB to APB BUS Bridge verilog code AMBA AXI designer user guide AMBA AXI to APB BUS Bridge verilog code FD001 User Guide ARM DUI 0333 0x00000212 PDF

    RGB to CSI-2

    Abstract: CAMERA PARALLEL RGB TO MIPI CSI-2 Camera Module CSI2 MIPI csi-2 SpeedTags CMOS Camera Module CSI RGB TO MIPI cSI2 MIPI TO bt 601 MIPI csi 5 MP camera module 2 MP
    Contextual Info: IP Product Brief Applications • Mobile Phones • Portable Media camerIC - 18 IP core Players Camera Processor IP Cores up to 18 Megapixels • Netbook PCs • CMOS Sensor Module The camerIC-18 camera processor IP cores are a complete 18 megapixel MP video and still


    Original     		camerIC-18 SiI-PB-1066 RGB to CSI-2 CAMERA PARALLEL RGB TO MIPI CSI-2 Camera Module CSI2 MIPI csi-2 SpeedTags CMOS Camera Module CSI RGB TO MIPI cSI2 MIPI TO bt 601 MIPI csi 5 MP camera module 2 MP PDF

    zl54

    Abstract: zl58 YL162 lcd T1Z12 Diode t1z75 T1Y30 t1z47 ARM cortex R7 processor ZL56 t1z24
    Contextual Info: Core Tile for ARM Cortex -R4F HBI-0196 User Guide Copyright 2009-2010 ARM Limited. All rights reserved. ARM DUI 0441B ID071010 Core Tile for ARM Cortex-R4F User Guide Copyright © 2009-2010 ARM Limited. All rights reserved. Release Information


    Original     		HBI-0196 0441B ID071010) ID071010 zl54 zl58 YL162 lcd T1Z12 Diode t1z75 T1Y30 t1z47 ARM cortex R7 processor ZL56 t1z24 PDF

    Xilinx Spartan6 Design Kit

    Abstract: vhdl code for spartan 6 AMBA AXI specifications Xilinx Virtex6 Design Kit AMBA AXI verilog code spdif input processor FIFO axi wrapper virtex5 vhdl code for dvi controller vhdl code for spartan 6 audio VESA Video Electronics Standards Association Local Bus
    Contextual Info: LogiCORE IP DisplayPort v3.1 DS802 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP DisplayPort™ interconnect protocol is designed for transmission and reception of serial-digital video for consumer and professional


    Original     		DS802 Xilinx Spartan6 Design Kit vhdl code for spartan 6 AMBA AXI specifications Xilinx Virtex6 Design Kit AMBA AXI verilog code spdif input processor FIFO axi wrapper virtex5 vhdl code for dvi controller vhdl code for spartan 6 audio VESA Video Electronics Standards Association Local Bus PDF

    ARM pin configuration

    Abstract: Coresight 6-pin JTAG AMBA AXI specifications ARM microcontroller ARM1136J-S jazelle ahb to axi
    Contextual Info: ARM DS-5 Glossary Version 5.2 ARM DUI 0490B ID100410 Copyright 2010 ARM. All rights reserved. Non-Confidential 1-1 ARM® DS-5™ Glossary Copyright © 2010 ARM. All rights reserved. Release Information The following changes have been made to this book.


    Original     		0490B ID100410 32-bit ARM pin configuration Coresight 6-pin JTAG AMBA AXI specifications ARM microcontroller ARM1136J-S jazelle ahb to axi PDF

    ARM1136J-S

    Abstract: state machine for axi to apb bridge 6-pin JTAG state machine for ahb to apb bridge basic architecture of ARM Processors trustzone thumb2 AMBA AHB protocol for ARM 7 AMBA AXI to APB BUS Bridge AMBA AXI specifications
    Contextual Info: ARM DS-5 Glossary Copyright 2010 ARM. All rights reserved. ARM DUI 0490A ID070310 ARM® DS-5™ Glossary ARM DS-5 Glossary Copyright © 2010 ARM. All rights reserved. Release Information The following changes have been made to this book. Table 1 Change History


    Original     		ID070310) 32-bit ID070310 ARM1136J-S state machine for axi to apb bridge 6-pin JTAG state machine for ahb to apb bridge basic architecture of ARM Processors trustzone thumb2 AMBA AHB protocol for ARM 7 AMBA AXI to APB BUS Bridge AMBA AXI specifications PDF

    difference between arm7 arm9 arm11 cortex

    Abstract: DSA09-PRDC-008772 PR430-PRDC-011726 ARM DII 0143 AMBA Network Interconnect NIC-301 Implementation Guide "coresight design kit" NIC-301 PR430-PRDC-011743 verilog code for dual port ram with axi interface ARM JTAG cortex a9 coresight
    Contextual Info: CoreSight Technology System Design Guide Copyright 2004, 2007, 2010 ARM Limited. All rights reserved. ARM DGI 0012D ID062610 CoreSight Technology System Design Guide Copyright © 2004, 2007, 2010 ARM Limited. All rights reserved. Release Information


    Original     		0012D ID062610) 32-bit ID062610 difference between arm7 arm9 arm11 cortex DSA09-PRDC-008772 PR430-PRDC-011726 ARM DII 0143 AMBA Network Interconnect NIC-301 Implementation Guide "coresight design kit" NIC-301 PR430-PRDC-011743 verilog code for dual port ram with axi interface ARM JTAG cortex a9 coresight PDF