ALTERA 48-MACROCELL APPLICATION Search Results

EPM5130

Abstract: 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130
Contextual Info: EPM5130 EPLD □ □ Features □ □ □ □ □ □ □ High-density, 128-macrocell, general-purpose MAX 5000 EPLD 128 m acrocells optim ized for pin-intensive applications, easily integrating over 60 TTL MSI and SSI components High-speed multi-LAB architecture

EPM5130

Abstract: EPM5130A-15 74N10
Contextual Info: EPM5130 EPLD Features • ■ ■ ■ ■ ■ ■ ■ ■ High-density, 128-macrocell, general-purpose MAX 5000 EPLD 128 macrocells optimized for pin-intensive applications, easily integrating over 60 TTL MSI and SSI components High-speed multi-LAB architecture

EPM5130

Abstract: LD128
Contextual Info: EPM5130 EPLD Features □ □ □ □ □ □ u □ High-density 128-macrocell general-purpose M A X 5000 E P L D 128 m acrocells optim ized for pin-intensive applications, easily integrating over 60 T T L M SI and SSI components H igh pin count for 16- or 32-bit data paths

AF14

Abstract: EPM9320 EPM9560 280-Pin
Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family February 1998, ver. 5.01 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

EPM9320

Abstract: EPM9560
Contextual Info: MAX 9000 Programmable Logic Device Family June 1996, ver. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

epm9320

Abstract: AF14 EPM9560
Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family December 2002, ver. 6.4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

AF14

Abstract: EPM9320 EPM9560
Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family October 2001, ver. 6.1 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

EPM5192

Contextual Info: EPM5192 EPLD Features H • ■ ■ ■ Figure 20. EPM5192 Package Pin-Out Diagrams Package outlines not drawn to scale. See Tables 8 and 9 in this data sheet fo r pin-out information. Windows in ceramic packages only. 0 D 3 z> D o û 5 2 2 § § § § § > iillo 0 § § § i° °

AF14

Abstract: EPM9320 EPM9560
Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family July 1999, ver. 6.01 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

AF14

Abstract: EPM9320 EPM9560
Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family November 2001, ver. 6.3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

M9000

Abstract: AF14 EPM9320 EPM9560 programming hardware manufacturers EPM9320 Transition
Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family June 2003, ver. 6.5 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

Contextual Info: M AX 9000 Programmable Logic Device Family June 1996, VBr. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ H igh-perform ance CM OS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array M atrix

Date Code Formats Altera EPF10K

Abstract: ep22v10 5962-9061102XA 5962-8854901xa 8686401LA 5962-8686401LA lift controller in vhdl ALTERA PART MARKING EPM7160 EPX780 transistor b2020
Contextual Info: Introduction Contents March 1995 Introduction The PLD Advantages of Altera

51h11

Abstract: C1058
Contextual Info: EPM 5128 E PLD Features • ■ ■ ■ ■ ■ Figure 14. EPM5128 Package Pin-Out Diagrams Package outlines not drawn to scale. See Tables 4 and 5 in this data sheet fo r pin-out information. Windows in ceramic packages only. , nnnnnnnnnnnnnnnnn i/o c I/O c

epm5064

Abstract: EPM5130 EPM5128 APPLICATION NOTE CERAMIC CHIP CARRIER LCC 68 socket EPM5130 adapter
Contextual Info: MAX 5000 Programmable Logic Device Family May 1999, ver. 5 F e a tu r e s. Data Sheet * • ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array Matrix MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

P6102

Abstract: EP6101-10
Contextual Info: Classic EPLD Family J a n u ary 1998. v er. J Features Data S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogram m ing w ith advanced, non-volatile

ep910 programmer

Abstract: EP610 programmer EPLD EP610-25 EP1810 EP610-15 EP610-20 EP610-30 EP910 K925
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

F1H16

Abstract: EPM 5192 epm5192 MSI MS-5 IC LM 384 gn
Contextual Info: EPM 5192 EPLD F e a tu re s • High-density, 192 macrocell, general-purpose M AX 5000 EPLD, easily integrating com plete logic boards into a single package High-speed m ulti-LAB architecture tpD as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz

16 bit data bus using vhdl

Abstract: AS 108-120 MACH Programmer 1 wire verilog code 144-Pin PLCC/TQFP Package Pin-Out Diagram EPM3256A bidirectional shift register vhdl IEEE format Block diagram of 8-1 multiplexer design logic loadable counter 32 Bit loadable counter and schematics
Contextual Info: MAX 3000A Programmable Logic Device Family July 1999, ver. 1.01 Features. Data Sheet • ■ Preliminary Information ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, low-cost CMOS EEPROM-based programmable logic devices PLDs built on a Multiple Array MatriX (MAX®)

ieee 1149.7

Abstract: BGA 168 AF5A
Contextual Info: MAX 9000 Programmable Logic Device Family F e b ru a ry 1998. F e a tu re s . • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array Matrix (MAX ) architecture

EPM7160 Transition

Abstract: EPM7160-3 EPM7160 PLMJ7160-84 single one jk flipflop EPM7160-1 EPM7160-2 E7041 5628E
Contextual Info: EPM7160 EPLD AN b rs rA \ High-Performance 160-Macrocell Device Data Sheet September 1992, ver. 2 Features □ Preliminary Information □ □ □ □ □ □ □ □ □ □ High-density, erasable CMOS EPLD based on second-generation Multiple Array MatriX MAX architecture

EPM5130

Abstract: EPM5192 EPM5064 EPM5032 EPM5032-15 EPM5064-1 EPM5128 ALTERA MAX 5000 EPM5064-2 ALTERA MAX 5000 programming
Contextual Info: MAX 5000 Programmable Logic Device Family June 1996, ver. 3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ Advanced Multiple Array MatriX MAX 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays

EPM5130

Abstract: J-Lead, EPM5128 APPLICATION NOTE ALTERA MAX 5000 MAX5000 macrocell Altera EPM5128 EPM5064-1
Contextual Info: MAX 5000 M M M & Programmable Logic Device Family , J a n u a r y 1 9 9 8 . v e r. 4 F e a tu re s . D a ta S h e e t m • ■ ■ Table 1. MAX5000 Device Features EPM5032 EPM5064 EPM5128 EPM5130 EPM5192 Usable gates 600 1,250 2,500 2,500 3,750 Macrocells

l9170

Abstract: EPM7000a EPM7000AE EPM7032AE EPM7064AE EPM7128A EPM7256A EPM7512AE C2719 EPM7000
Contextual Info: MAX 7000A Includes MAX 7000AE Programmable Logic Device Family October 1998, ver. 1.2 Data Sheet Features. • ■ Preliminary Information ■ ■ ■ ■ ■ ■ ■ ■ Formerly known as Michelangelo devices High-performance CMOS EEPROM-based programmable logic