ALTERA 28NM DEVICE Search Results

Parallel FIR Filter

Abstract: FPGA IMPLEMENTATION of Multi-Rate FIR OPTIMIZED FPGA IMPLEMENTATION OF MULTI-RATE FIR Altera 28-nm Portfolio DSP processor latest version in 2010 FIR FILTER implementation on fpga how dsp is used in radar radar fir filter Signal Path Designer 28nm
Contextual Info: Implementing FIR Filters and FFTs with 28-nm Variable-Precision DSP Architecture WP-01140-1.0 White Paper Across a range of applications, the two most common functions implemented in FPGA-based high-performance signal processing are finite impulse response FIR

matlab code for radix-4 fft

Abstract: matlab code for half adder FPGA "video wall" FFT 1024 point matlab code using 64 point radix 8 matlab code for fft radix 4 matlab code for mimo wireless radar fir filter radar dsp processor FIR filter matlaB simulink design
Contextual Info: Accelerating DSP Designs with the Total 28-nm DSP Portfolio WP-01136-1.0 White Paper Implementing digital signal processing DSP datapaths with different performance, precision, intellectual property (IP), and development flows is challenging and laborintensive. As more and more high-performance DSP datapaths are implemented on

matrix circuit VHDL code

Abstract: led matrix 32X32 vhdl code for cordic LU decomposition vhdl code for FFT 32 point 32x32 multiplier verilog code 64x64-bit ieee floating point multiplier verilog verilog code for matrix multiplication inverse trigonometric function vhdl code vhdl code for cordic multiplication
Contextual Info: Achieving One TeraFLOPS with 28-nm FPGAs WP-01142-1.0 White Paper Due to recent technological developments, high-performance floating-point signal processing can, for the first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations.

format .rbf

Abstract: FIPS-197 3A991 AN425 BR1220 BR2477A
Contextual Info: Using the Design Security Features in Altera FPGAs AN-556-2.0 Application Notes This application note describes how you can use the design security features in Altera 40- and 28-nm FPGAs to protect your designs against unauthorized copying, reverse engineering, and tampering of your configuration files. This application note

tcam

Abstract: ternary content addressable memory 100GbE Altera Stratix V datasheets of optical fpgas 100g phy interlaken network processor receiver ber fec 100G 40GBASE-R 10Gbase-kr transmitter
Contextual Info: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs WP-01128-1.1 White Paper As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want

Contextual Info: Using the Design Security Features in Altera FPGAs 2013.06.19 AN-556 Feedback Subscribe This application note describes how you can use the design security features in Altera 40- and 28-nm FPGAs to protect your designs against unauthorized copying, reverse engineering, and tampering of your

b 103g

Abstract: interlaken ternary content addressable memory WP-01127-1 computer networking diagram Double high-speed switching diode optical switch fabric interlaken network processor tcam Altera Stratix V
Contextual Info: Integrating 100-GbE Switching Solutions on 28-nm FPGAs WP-01127-1.1 White Paper With high-speed 100-GbE communication network standards converging, switching functions play a key role in the smooth functioning of the Internet. The aggregated network traffic doubles every six months and grows in complexity as it is transported

ROADM

Abstract: Altera Stratix V muxponder 2.5G DWDm OC192
Contextual Info: White Paper Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs The rapid growth in bandwidth required to support video and broadband wireless is straining communication networks. The current 10-Gbit OTN infrastructure is facing bandwidth exhaustion as the channels approach their

OTN SWITCH

Abstract: OC192 muxponder stratixv
Contextual Info: Increasing Design Functionality with Partial and Dynamic Reconfiguration in 28-nm FPGAs WP-01137-1.0 White Paper The density of FPGAs has grown with each process node shrink. Compared to previous generations of FPGAs, the extra density, coupled with features such as

precision

Contextual Info: Enabling High-Performance, High-Precision Signal Processing 28-nm Variable-Precision DSP Block Architecture More than ever, digital signal processing DSP applications need high performance and high precision, in the greater than 18-bit range. That's why the DSP capabilities of FPGAs are ideal. In our

Contextual Info: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions AN-661-3.0 Application Note This application note describes the flow for implementing fractional phase-locked loop PLL reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm

RAM SEU

Abstract: AN357 M20K engine injection controller altera MTBF Altera Stratix V Altera 28nm Device
Contextual Info: Enhancing Robust SEU Mitigation with 28-nm FPGAs WP-01135-1.0 White Paper Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability, high-reliability, and safety-critical systems. However, along with

Optical SAS QSFP

Abstract: CEI-6G-LR 28G-SR QSFP 32G CEI-11G QSFP QSFP CONNECTOR QSFP 25G ibis sata interlaken
Contextual Info: White Paper Extending Transceiver Leadership at 28 nm High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system bandwidth by attaining higher data

28HP

Abstract: pcie gen3 10GBASE-KR class 10 up board Datasheet 2012 CPRI Multi Rate datasheets of optical fpgas germanium power devices corporation germanium small signal power devices corporation pcie X1 edge connector pcie X8
Contextual Info: Introducing Innovations at 28 nm to Move Beyond Moore’s Law WP-01125-1.1 White Paper In addition to processing techniques, FPGA innovations allow Altera to move beyond Moore’s Law to meet higher bandwidth requirements while meeting cost and power budgets. Altera’s Stratix V FPGAs provide breakthrough bandwidth via 28-Gbps

pcie gen3

Abstract: 10GBASE-KR interlaken optical 400G CPRI multi rate 400G M20K 28Gbps 100g phy Stratix V
Contextual Info: Stratix V FPGAs: Built for Bandwidth Meeting Bandwidth Demands Mobile video, audio/video streaming, cloud computing—these are just a few of the many applications driving up bandwidth demands for the underlying communications infrastructure. To be successful, your next-generation products

Altera Stratix V

Abstract: QSFP 40G transceiver CEI-28G interlaken optical 400G QSFP 400G M20K JTRS QSFP 10G
Contextual Info: Fulfilling Technology Needs for 40G–100G Network-Centric Operations and Warfare WP-01138-1.1 White Paper The development and deployment of network-centric operations and warfare NCOW to integrate and connect the military’s many separate networks relies on

QSFP28 I2C

Contextual Info: Arria 10 Device Overview 2013.09.04 AIB-01023 Subscribe Feedback Altera’s Arria FPGAs and SoCs deliver optimal performance and power efficiency in the midrange. By using TSMC's 20-nm process technology on a high-performance architecture, Arria 10 FPGAs and SoCs

Altera Stratix V

Abstract: 10G EPON EPON based VOIP by Cisco 10g EPON ONU EPON ONU 10g EPON olt Optical-Splitter MDU FTTH design 10G-EPON 10G-EPON ONU
Contextual Info: Implementing Next-Generation Passive Optical Network Designs with FPGAs WP-01143-1.1 White Paper Passive optical network PON technology is emerging as the key access technology, as it has a scalable and cost-effective architecture to satisfy the ever-growing

military radars

Abstract: full subtractor implementation using multiplexer radar, ACC WC201 signal path designer
Contextual Info: White Paper Enabling High-Precision DSP Applications with the FPGA Industry’s First Variable-Precision Architecture The silicon digital signal processing DSP architecture of the FPGA can make a big difference when implementing complex signal-processing algorithms. Altera’s Stratix V FPGAs, with the variable-precision DSP block

ARm cortexA9 GPIO

Abstract: arm cortex a7 mpcore AV-51001 cortex-a9 M10K fd7k interlaken network processor D5250
Contextual Info: Arria V Device Overview 2013.01.11 AV-51001 Subscribe Feedback The Arria V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from the lowest power for 6 gigabits per second Gbps and 10 Gbps applications, to the highest mid-range FPGA

100GBASE-R

Abstract: QSFP 40G transceiver 40GBASE-R CPRI multi rate gearbox pcie gen3 QSFP optical active cable QSFP M20K 5SGX
Contextual Info: Stratix V Device Family Overview SV51001-1.3 This document provides an overview of the Stratix V device features. Many of these features are enabled in the Quartus ® II software version 10.0. The remaining features will be enabled in future versions of the Quartus II software.

Contextual Info: Arria V Device Overview 2013.05.06 AV-51001 Subscribe Feedback The Arria V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from the lowest power for 6 gigabits per second Gbps and 10 Gbps applications, to the highest mid-range FPGA

HF35-F1152

Abstract: KF40-F1517 5sgxa3 eye-q 400 NF40-F1517 interlaken gf35 NF45 KF35-F1152
Contextual Info: Stratix V Device Family Overview January 2011 SV51001-1.6 SV51001-1.6 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus ® II software version 10.1. The remaining devices and features will be enabled in future versions of the

SV51001-3

Abstract: interlaken 100GBASE-R 5SGXBB HF35-F1152
Contextual Info: Stratix V Device Overview June 2012 SV51001-3.0 SV51001-3.0 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus® II software version 12.0. The remaining devices and features will be enabled in future versions of