AGERE 840 Search Results

9214a

Contextual Info: Preliminary Data Sheet August 2002 L9214A/G Low-Cost Ringing SLIC Introduction Applications The Agere Systems Inc. L9214 is a subscriber line interface circuit that is optimized to provide a very low-cost solution for short- and medium-loop applications. This device provides the complete set of line

l9214

Abstract: GR-909 L9214A L9214G MO-220 T7504 T8536 rgn 1064 agere 840
Contextual Info: Preliminary Data Sheet October 2001 L9214A/G Low-Cost Ringing SLIC Introduction Applications The Agere Systems Inc. L9214 is a subscriber line interface circuit that is optimized to provide a very low-cost solution for short- and medium-loop applications. This device provides the complete set of line

TMPRFE2G5

Abstract: MARS2G5 bey34 DIODE BA40 LVTTL25
Contextual Info: Hardware Design Guide September 8, 2004 MARS2G5 P-VC-XTRM TMPRFE2G5 Datamapper 2488/622/155 Mbits/s SONET/SDH x 10/100/1000 Mbits/s Ethernet 1 Introduction The documentation package for the Datamapper device consists of the following documents, available on a password protected website:

LSP2908

Abstract: agere 840
Contextual Info: a8e re AdLib systems OCR Evaluation Advance Data Sheet September 2001 LSP2908 8-Channel, High-Voltage Driver Features . Eight amplifier channels in one package . Outputs from -298 V to +160 V per channel . Programmable output current limit 100 pA to 500 j A

LCK4801

Abstract: LCK4802 MPC998
Contextual Info: Advance Data Sheet December 2001 LCK4802 Low-Voltage PECL Differential Clock General Features The LCK4802 is a low-voltage, 3.3 V PECL differential clock synthesizer. The LCK4802 supports two differential PECL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to

LCK4801

Abstract: MPC998 2274a
Contextual Info: Preliminary Data Sheet December 2001 LCK4801 Low-Voltage HSTL Differential Clock General Features The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to

M-LSP2908

Abstract: LSP2908
Contextual Info: Advance Data Sheet September 2001 LSP2908 8-Channel, High-Voltage Driver Features • Eight amplifier channels in one package ■ Outputs from –298 V to +160 V per channel ■ ■ condition that |VHP – VHN| ≤ 300 V. Voltage gain is set by external resistors. Each amplifier can output

7495 data sheet

Abstract: LCK4801
Contextual Info: Preliminary Data Sheet July 2001 LCK4801 Low-Voltage HSTL Differential Clock General Features The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to

gtx2 0135

Contextual Info: Preliminary Data Sheet May 2002 T8533/T8534 Quad Programmable Codec and Echo Canceller Features • ■ Includes codec, termination impedance, and echo canceller in one device for line card applications Programmable µ-law, linear, or A-law PCM input and output ITU-T G.712 compliant

25D30

Contextual Info: Data Sheet July 2002 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

parabolic antenna

Abstract: LNA x-band 8910A 302opt apc back-ups 500 rs apc back-ups 800 rs diagram X-band lna hpa L-band
Contextual Info: Data Sheet, Rev. 1 September 2001 System 8000 Fiber-Optic Interfacility Links Description Designed to interface directly with earth station equipment, the multifaceted System 8000 interfacitlity link offers a wide variety of unique, site-specific interconnectivity solutions for

PUB43801

Abstract: T5504 T7504
Contextual Info: Data Sheet February 2002 T7504 and T5504 Quad PCM Codecs with Filters Features Description • 5 V only ■ Low-power, latch-up-free CMOS technology — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation ■ Automatic master clock frequency selection

pin diagram of ic 7495

Abstract: data sheet ic 7495 pin diagram of ic 7495 A pin diagram of ic 7495 pin diagram data sheet of ic 7495 ALL DATA SHEET ic 7495 shift registers 7495 data sheet pin diagram of ic 555 pin diagram of 7495
Contextual Info: Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Features • ■ Includes codec, termination impedance, and echo canceller in one device for line card applications Programmable µ-law, linear, or A-law PCM input and output ITU-T G.712 compliant

NEC Technologies

Contextual Info: Data Sheet November 2006 USS2000 Four-Port USB2.0 PCI-to-USB Host Controller 1 Features 2 Applications „ 32-bit, 33 MHz PCI interface compliant with PCI Local Bus Specification Revision 2.2. „ Seamless integration with 3 V or 5 V PCI-based computer products.

Contextual Info: Preliminary Data Sheet August 2002 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

EC60825-1

Abstract: EC60825 TD1611 STM-16 TD16L1 agilent receiver OC-48 1EC60825-1 transmitter agilent oc 192 agere 840 demultiplexer outline
Contextual Info: a8e re AdLib OCR Evaluation systems Advance Data Sheet May 2002 TD16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer Description The TD16-type transponder performs straightforward, bit-level parallel-to-serial converting in the

Agere read channel

Abstract: DATA Sheet IC 555 84 PLCC pin configuration data sheet book ic 555 Ringing Subscriber Line Interface Circuit NXP T8533 T8534 T8535B T8536B T8538B
Contextual Info: Preliminary Data Sheet September 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

ECHO canceller IC

Abstract: L7591 L9215G T8534
Contextual Info: Preliminary Data Sheet April 2002 T8534 Quad Programmable Codec and Echo Canceller Features • ■ Includes codec, termination impedance, and echo canceller in one device for line card applications Programmable µ-law, linear, or A-law PCM input and output ITU-T G.712 compliant

8503

Abstract: CA 3140 OP AMP PUB43801 T8502 T8503
Contextual Info: Data Sheet February 2002 T8502 and T8503 Dual PCM Codecs with Filters Features • +5 V only ■ Two independent channels ■ Pin-selectable receive gain control ■ Pin-selectable µ-law or A-law companding ■ Automatic powerdown mode ■ Low-power, latch-up-free CMOS technology

LCK4802

Abstract: BA 658 pll 564
Contextual Info: Preliminary Data Sheet July 2001 LCK4802 Low-Voltage PECL Differential Clock General Features The LCK4802 is a low-voltage, 3.3 V PECL differential clock synthesizer. The LCK4802 supports two differential PECL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to

Contextual Info: Data Sheet May 2004 FW322 06 T100 1394A PCI PHY/Link Open Host Controller Interface Features „ 1394a-2000 OHCI link and PHY core function in a single device: — 100-pin TQFP package also available in a leadfree package; see ordering information on page 85.

FW3227

Contextual Info: Data Sheet November 2004 FW322 06 T100 1394A PCI PHY/Link Open Host Controller Features „ „ „ supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic — Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders — While unpowered and connected to the bus, will

L7583

Abstract: L7583B L8567 T7507 pub 43801
Contextual Info: Data Sheet August 1999 T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance Features • 5 V only ■ Low-power, latch-up-free CMOS technology: — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation

data sheet ic 7495

Abstract: gtx2 0135 0124C 7495 ic data sheet DATA Sheet IC 555 digital clock ckt diagram ic 7495 data sheet pin diagram of ic 7495 pin diagram of ic 7495 A Ringing Subscriber Line Interface Circuit NXP
Contextual Info: Preliminary Data Sheet May 2001 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame