0124C Search Results

pin diagram of ic 7495

Abstract: T8533 T8534 T8535B T8536B T8538B
Contextual Info: Preliminary Data Sheet June 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

intel i386 ex circuit diagram

Abstract: intel 80368 Instruction set Architecture i386 ex board M82384 i386 dx ICE-386 271052 271062 i386 SL M8088
Contextual Info: SñE J> • intei 462bl75 D I S H E D 17T ¡ITL1 INTEL CORP ÜP/PRPHLS ' T ' L t cv - n - y t - f MILITARY ¡386 HIGH PERFORMANCE 32-BIT MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Flexible 32-Bit Microprocessor — 8, 16, 32-Bit Data Types — 8 General Purpose 32-Bit Registers

data sheet ic 7495

Abstract: gtx2 0135 0124C 7495 ic data sheet DATA Sheet IC 555 digital clock ckt diagram ic 7495 data sheet pin diagram of ic 7495 pin diagram of ic 7495 A Ringing Subscriber Line Interface Circuit NXP
Contextual Info: Preliminary Data Sheet May 2001 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Agere read channel

Abstract: DATA Sheet IC 555 84 PLCC pin configuration data sheet book ic 555 Ringing Subscriber Line Interface Circuit NXP T8533 T8534 T8535B T8536B T8538B
Contextual Info: Preliminary Data Sheet September 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Contextual Info: T8535B/T8536B Quad Programmable Codec Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5 V operation Per-channel programmable gains, equalization, termination impedance, and hybrid balance Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

pin diagram of ic 7495

Abstract: data sheet ic 7495 T8533 T8534 T8535B T8536B T8538B
Contextual Info: Preliminary Data Sheet July 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Contextual Info: Preliminary Data Sheet August 2001 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

data sheet ic 7495

Abstract: T8538 0071A 321AL
Contextual Info: Advance Data Sheet October 2000 T8538A Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes — Up to 256 time slots per frame

T8533

Abstract: T8534 T8535B T8536B T8538B
Contextual Info: Data Sheet March 2002 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

grx2

Contextual Info: T8538B Quad Programmable Codec Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.3 V operation Per-channel programmable gains, equalization, termination impedance, and hybrid balance Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

pin diagram of ic 7495

Abstract: T8533 T8534 T8535A T8536A
Contextual Info: Preliminary Data Sheet March 2001 T8535A/T8536A Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

digital clock ckt diagram

Abstract: grx2 T8536B T8538B
Contextual Info: Preliminary Data Sheet August 2001 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame

Contextual Info: Features • ■ ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame — Supports PCM data rates of 512 kbits/s to 16.384 Mbits/s — Double-clock mode timing compatible with ISDN