ABORT Search Results

Z8000

Abstract: z8530 8086 logic diagram dc av converter Z8030 8086 interrupt structure 8086 structure interrupt structure of 8086 CRC-16 Z-636
Contextual Info: Z8030/Z8530 Serial Communications Controller DISTINCTIVE CHARACTERISTICS • Programmable Synchronous Modes - SDLC and HDLC, and SOLC loop supported with frame control, zero insertion and deletion, abort, a residue handling - CRC-16 and CCITT generators and checkers

T5 transistor TO-247

Abstract: IRG4PSC71K
Contextual Info: PD - 91683A IRG4PSC71K PRELIMINARY Short Circuit Rated UltraFast IGBT INSULATED GATE BIPOLAR TRANSISTOR C Features • Hole-less clip/pressure mount package compatible with TO-247 and TO-264, with reinforced pins • High abort circuit rating IGBTs, optimized for

IRG4PSC71KD

Contextual Info: PD - 91684A PRELIMINARY IRG4PSC71KD Short Circuit Rated UltraFast IGBT INSULATED GATE BIPOLAR TRANSISTOR WITH ULTRAFAST SOFT RECOVERY DIODE C Features • Hole-less clip/pressure mount package compatible with TO-247 and TO-264, with reinforced pins • High abort circuit rating IGBTs, optimized for

ST10Nm

Abstract: 32000K
Contextual Info:  STLC5465B MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . . . . . . . . . . . . . 32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS 4 OR

12v and 5v regulated power supply circuit diagram

Abstract: L6605 L6605D SO20
Contextual Info: L6605 SMART CARD INTERFACE 8 DIFFERENT VPP OUTPUT VOLTAGE LEVELS VPP, VCS RISE AND FALL TIME FULL SPEC WITH ISO/IEC 7816-3 POWER SUPPLY OUTPUT FOR MEMORY CARD 5V/80mA POWER ON/OFF RESET AUTOMATIC SWITCH-OFF OF ALL FUNCTIONS IF THE REGULAR OPERATION IS ABORTED

2498A

Contextual Info: Errata • • • • • • Increased Interrupt Latency Interrupts Abort TWI Power-down TWI Master Does not Accept Spikes on Bus Lines TWCR Write Operations Ignored PWM not Phase Correct TWI is Speed Limited in Slave Mode 6. Increased Interrupt Latency

ana60

Abstract: AFM2 AFM8 hdlc INTEL 386EX TDA 1512 STLC5466 TQFP176 Motorola CMOS Dynamic RAM 1M x 1 1989
Contextual Info: STLC5466 64 CHANNEL-MULTI HDLC WITH N X 64KB/S SWITCHING MATRIX ASSOCIATED • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 64 TX HDLCs with broadcasting capability and/ or CSMA/CR function with automatic restart in case of Tx frame abort

PIR CONTROLLER LP 0001

Abstract: MOSTEK 38P70 8401h mil-std-1750 38P70 a00b F9450-15DC 5019 38p70 mostek 3D IC
Contextual Info: v ' : ' C-. • ' S"ñ 3 P A IR Ç H IL D A Schlumberger Company l i C- Ù - 'l O rU L ^ I 001193 jt 1 í¡,cO Preliminary Data Sheet - November 1985 DESCRIPTION y F9450 High-Performance 16-Bit Bipolar Microprocessor Microprocessor Product Built-In Self-Test, Fault Handling, and Abort

motorola 6800 8bit hardware architecture

Abstract: 6800 intel microprocessor pin diagram motorola 6800 8bit software architecture AFM8 VCXO 2048khz crystal 68020-16 80C186-16 AFM2 ana61 control unit of 68020
Contextual Info:  STLC5465B MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . . . . . . . . . . . . . 32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS 4 OR

Contextual Info: PD - 91683B IRG4PSC71K Short Circuit Rated UltraFast IGBT INSULATED GATE BIPOLAR TRANSISTOR C Features • Hole-less clip/pressure mount package compatible with TO-247 and TO-264, with reinforced pins • High abort circuit rating IGBTs, optimized for motorcontrol

2RD6

Abstract: RB35 TDNB0
Contextual Info: BACK HDLC Device HDLC Controller TXC-05101C DATA SHEET Preliminary FEATURES DESCRIPTION • HDLC ISO/OSI level 2 functions, including internal flag, abort, and zero deletion/insertion The TranSwitch TXC-05101C is a high speed, High Level Data Link Controller HDLC designed to send

datasheet arm

Abstract: ARM bus ARM circuit ARM processor data sheet LDR -03 thumb mode instructions and its limitations branch conditional unconditional instruction
Contextual Info: 1 11 Index A B Abort data 3-12 during block data transfer 4-44 prefetch 3-12 Abort mode 3-4 ADC ARM instruction 4-11 THUMB instruction 5-3, 5-11 ADD ARM instruction 4-11 THUMB instruction 5-3, 5-7, 5-9, 5-28, 5-30 with Hi register operand 5-13 address bus

MAP32

Contextual Info: CL-CD2431 A dvanced M ulti-Protocol C om m unications Controller 1CIRRUS LOGIC Bit Index Numerics AbortTx 116-118 AdMd[1:0] 86 AFLO 86 A lti 93 AppdCmp 118 Append 150 DisRx 113 DisTx 113 DpIIEn 110 Dpllmd[1:0] 1 DSR 123 DsrAE 88-90 DSRChg 147 D S R od97 DSRzd 96

VCXO 2048khz crystal

Abstract: ana61 ana60 hdlc ITS31 NCR Microelectronics Division 80C186 80C188 PQFP160 STLC5464
Contextual Info: STLC5464 MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED . . . . . . . . . . . . . . 32 TxHDLCs WITH BROADCASTING CAPABILITY AND/OR CSMA/CR FUNCTION WITH AUTOMATIC RESTART IN CASE OF TX FRAME ABORT 32 RxHDLCs INCLUDING ADDRESS RECOGNITION 16 COMMAND/INDICATE CHANNELS 4 OR

AM85C30

Contextual Info: FINAL a Advanced Micro Devices Am85C30 Enhanced Serial Communications Controller DISTINCTIVE CHARACTERISTICS — Programmable CRC generators and checkers • Fastest data rate of any Am8530 — SDLC/HDLC support includes frame control, zero insertion and deletion, abort, and residue

Contextual Info: Freescale Semiconductor Mask Set Errata MPC560XS_2M25V Rev. 3, 27 SEPT 2012 Mask Set Errata for Mask 2M25V Introduction This report applies to mask 2M25V for these products: • MPC560XS Errata ID Errata Title 4168 ADC: "Abort switch" aborts the ongoing injected channel as well as the upcoming normal channel

sda 5708

Contextual Info: Freescale Semiconductor Mask Set Errata KINETIS_4N30D Rev 07 AUG 2013 Mask Set Errata for Mask 4N30D Introduction This report applies to mask 4N30D for these products: • KINETIS Errata ID Errata Title 2550 ADC: ADC abort conversion logic error 2776 CRC: May have incorrect CRC result when performing CRC 8-bit or 16-bit writes with transpose enabled.

E2613

Abstract: E2583 E2448 E25-9-6 DMX32 0M33Z Freescale - Kinetis E2550 IHI0014O E2575
Contextual Info: Freescale Semiconductor Mask Set Errata KINETIS_0M33Z Rev. 08 NOV 2010 Mask Set Errata for Mask 0M33Z Introduction This report applies to mask 0M33Z for these products: • KINETIS Errata ID Errata Title 2550 ADC: ADC abort conversion logic error 2547 DAC: 12-bit DAC buffer registers cannot be read.

TDA 9370

Abstract: AM85C30 am85c30 manual 80286 THOMPSON marking 0229 pnt2 53C80 80C286 WR10 microprocessor 80286
Contextual Info: FINAL a Am85C30 Advanced Micro Devices Enhanced Serial Communications Controller DISTINCTIVE CHARACTERISTICS — Programmable CRC generators and checkers • Fastest data rate of any Am8530 — SDLC/HDLC support includes frame control, zero insertion and deletion, abort, and residue

8N30

Contextual Info: Freescale Semiconductor Mask Set Errata KINETIS_8N30D Rev. 18 FEB 2013 Mask Set Errata for Mask 8N30D Introduction This report applies to mask 8N30D for these products: • KINETIS Errata ID Errata Title 2550 ADC: ADC abort conversion logic error 2776 CRC: May have incorrect CRC result when performing CRC 8-bit or 16-bit writes with transpose enabled.

Contextual Info: T ^ 5 - Ì 7 PUBLICATION D/234 PRELIMINARY INFORMATION PIN FUNCTIONS 1 Data change PIN CONFIGURATON 15 D10 28 lead Dual-in-Line 2 Power up reset 16 D11 3 Vss 17 D12 4 Alert reset 18 D13 5 Decode abort 19 Group digit ’O ’ 6 Preamble mode 20 All-call inh.

weitek FPU

Contextual Info: XL-8136 32-BIT PROGRAM SEQUENCING UNIT DATA SHEET January 1989 Features 32-BIT SIN G LE-CH IP SEQUENCIN G U NIT PARALLEL FETC H AND EXECUTE 32-bit code address bus 32-bit data address bus 33 X 32-bit on-chip stack On-chip instruction pipeline register STALL and ABORT logic to handle m em ory misses

IPDM41039S

Contextual Info: P PARADIGM Features: □ Fast A ccess and Cycle Times: 1 7 /2 0 ns Max □ Fully Synchronous Operation, Single Clock Control □ Clock Tim ed Writes w ith A synchronous Late Write Abort □ Registered A ddress Inputs □ C om m on Data Inputs and Data Outputs

Transistor A14

Abstract: a10 transistor
Contextual Info: Q S86448 High-Speed CMOS 64Kx4 SRAM with Address Register Q QS86448 A DV AN CE INFORMATION FE A TU R E S /B E N E FIT S • • • • • Fully synchronous, single clock operation 15ns/20ns/25ns/35ns Commercial Self timed write with late write abort Low power, high-speed QCMOS technology