A8 JZ Search Results

I-7017

Abstract: yc 236 ic str 5650 S0840 GKO 7J
Contextual Info: C1B/0:=#D/'/#3E=' 6=%8;/8F#.-. !"#$%&'#!"!!""#$%&' #*+,-.#/01#2.#$%&')()#*+,-2# ) P=0=G&') • @5.*-;,!5-&EV W Q>#(!+-0!)=,*!%)0.,*I*,-+E!-0;!E'.E,*I(5,;! ()%$&')0(X!-(!&E,!,0;!$(,*!0,;(!$5.*-;,(O

Contextual Info: LH5324500 FEATURES CMOS 24M 3M x 8/1.5M x 16 MROM PIN CONNECTIONS • 3,145,728 words (Byte mode) x 1,572,864 words (Word mode) x 8 bit organization 44-PIN SOP TOP VIEW S 1• A-I8 C 2 43 — I a 19 A17IZ 3 42 ^ A8 • Access time: 150 ns (MAX.) a7C 4 41 Zl Ag

Contextual Info: SMJ44C256 262,144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY 2 6 2 .1 4 4 x 4 Organization JD PACKAGE T O P V IE W Single 5-V Supply (10% Tolerance) D Q l[ 1 U 2 0 > s s 19 Ü D Q 4 DQ2[ 2 18 D DQ3 wC 3 17 ] CAS R ASd 4 16 3 5 5 A0[ 6 15 ] A8 A1[ 7 14 ] A 7

Scans-048

Abstract: LF BEX DSAGER00026
Contextual Info: f f l r i i a t B C C T Œ C K lf l «THKUHOBAXLatr. J£ I li I I i 17 Ab IS AIO 111 7CIGBHCE TPianBCtDZ nEnggm nawy 06 09 "IT " IS AO AI A2 A3 A4 A5 • A6 • A7 ■ A8 ■ A9 . AIO ■AH 05 06 ■ <_ËL - si 12 17 - CE Tamn^ o i nrnrvirr w r v, r ryrrv iihktt s b ¿ / g g ;

ZWS 6 controller

Abstract: 82C450 bt471
Contextual Info: •• •••«•a m m ••••• imm a M _ _ _*••••§_«••• ’t 7 v . n i r D Pinouts _ Pinouts £ jS y S ijjô u s r ,ÛQÛQÛÛ£ <<É paco; > û. eu a. o > ,U fejf^¿C/3POtM <-iOZüJ, JZ&Äi*hdi<ä3eof a. a. eu eu eu cl v> u u U u os os ü

2SD525

Abstract: AC75 HK1H
Contextual Info: T O S H I B A -CDISCRETE/OPTO} 9097250 TOSHIBA Ib <D I S C R E T E / O P T O ^ 1 ^ 0^7550 00G 7332 5 5òC 0 7 3 3 2 Üf'-jZ-/? SILICON PNP TRIPLE DIFFUSED TYPE PCT PROCESS) Unit in mm 1Q.3MAX. 0&6±O,2 POWER AMPLIFIER APPLICATIONS. FEATURES: • High Breakdown Voltage

54V25632A

Contextual Info: E2L0051-27-Z4 O K I Semiconductor Previous version: May. 1997 M SM 54V25632A 131,072-Word x 32-Bit x 2-Bank Synchronous Graphics RAM DESCRIPTION The MSM54V25632A is a synchronous graphics random access memory organized as 128 K words x 32 bits x 2 banks. This device can operate up to 100 MHz by using synchronous interface. In addition, it has 8-column

256Kx4 VRAM

Abstract: F8680 SADI 386dx circuit schematic SBD3 oba6 386dx schematic chips 65520 flat panel vga 386sx 386sx schematic
Contextual Info: Application Schematic Examples Application Schematic Examples This section includes schematic examples showing various 65525 interfaces. The schematics are broken down into four main groups for discussion: 1 System Bus Interface • PC/AT ISA 16-Bit) Bus

640NS

Contextual Info: HIGH–SPEED MICROCONTROLLER USER’S GUIDE SECTION 5: CPU TIMING XTAL2 The timing of the High–Speed Microcontroller is the area with the greatest departure from the original 8051 series. This section will briefly explain the timing and also compare it to the original.

R40 AH

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are

BI71

Contextual Info: HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM HITACHI ADE-203-223A Z Rev. 1.0 May. 30, 1996 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for

UA777

Contextual Info: ADE-203-223 B (Z) HM5283206 Series 131072-word x 32-bit x 2-bank Synchronous Graphic RAM Preliminary Rev. 0.2 Nov. 20, 1995 HITACHI All inputs and outputs signals refer to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column

Contextual Info: ADE-203-223 A (Z) * HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM Preliminary HITACHI — Self refresh (1024 refresh cycles: 16 ms) All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides

Contextual Info: ADE-203-199 A (Z) HM5221605 Series 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM Preliminary Rev. 0.1 Sep. 22, 1994 HITACHI All inputs and outputs are referred to the rising edge of the clock input. The HM5221605 is offered in 2 banks for improved performance.

mhtl

Contextual Info: HM5221605 Series 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-199A Z Rev. 1.0 Jun. 22,1995 Description All inputs and outputs are referred to the rising edge of the clock input. The HM 5221605 is offered in 2 banks for improved performance.

Contextual Info: HM5241605C Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI ADE-203-381B Z Rev. 2.0 Jan. 7, 1997 Description A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2 banks for improved performance.

74Ls962

Abstract: w10tk DM54LS962J DM74LS962 DM74LS962N J18A N18A
Contextual Info: DM54LS962/DM74LS962 National Semiconductor Corporation DM54LS962/DM74LS962 Dual Rank 8-Bit TRI-STATE Shift Registers General Description Features These circuits are TRI-STATE, edge-triggered, 8-bit I/O reg­ isters in parallel with 8-bit serial shift registers which are

mb818251

Abstract: 818251-70
Contextual Info: July 1994 Edition 2.2 FUJITSU DATA SHEET M B 8 1 8 2 5 1 -70/-80 2097,152 Bits 262,144 x 8 Bits Multi-port CMOS Dynamic RAM The Fujitsu MB818251 is a fully decoded dual port CMOS Dynamic RAM (DRAM) organized as 262,144 words by 8 bits dynamic RAM port and 512 words by 8 bits serial

Contextual Info: ADE-203-186A Z i HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM H IT A C H I All inputs and outputs are referred to the rising edge of the clock input. The HMS241605 is offered in 2 banks for improved performance. 3.3 V Power supply

M5216

Contextual Info: ADE-203-304 B (Z) HM5216805 Series HM5216405 Series 1048576-word x 8-bit x 2-bank Synchronous Dynamic RAM 2097152-word x 4-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising Aug. 4, 1995 Ordering Information edge of the clock input. The HM 5216805 Series,

77777AV

Abstract: R7F7
Contextual Info: H M 5 2 4 1 6 5 - 1 Preliminary 2 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605 is offered in 2 banks for improved performance. Features m Rev. 0.0 Jan. 27,1995

tney2

Abstract: HM5241 5241605
Contextual Info: HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605 is offered in 2 banks for improved performance. _ F e a tu re s •3.3V Power s u p p

Contextual Info: R F M MICRO-DEVICES RF2906 | Preliminary 4 3 3 M H Z PSK/FSK/ASK DATA TRANSCEIVER Typ ical A p plications • Wireless Meter Reading • W ireless Data Transceiver • Keyless Entry Systems • 4 3 3 MHz European ISM Band Equipment • Remote Controls • Battery Powered Portable Devices

HM5241

Abstract: HM5241605CTT15
Contextual Info: HM5241605C Series Preliminary 131,072-w ord x 16-bit x 2-bank Synchronous Dynam ic RAM H IT A C A ll inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2 banks for improved performance. Features • 3.3 V Power supply