A144 PACKAGE Search Results

AA0301

Abstract: SC11 DSP56302 SC10 SC12 D-6108 D2083
Contextual Info: SECTION 3 PACKAGING PIN-OUT AND PACKAGE INFORMATION This sections provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56302 is available in a144-pin Thin

transistor A144

Abstract: TQFP 144 PACKAGE A144 transistor data sheet A144 a144* transistor CERAMIC FLATPACK TQFP 32 PACKAGE B144 G145 U162
Contextual Info: 2.7 Package Diagrams 144-Pin Plastic Thin Quad Flat Pack TQFP A144 2-30 Package Diagrams 145-Pin Plastic Grid Array (Cavity Up) B144 145-Pin Grid Array (Cavity Up) G145 2-31 Package Diagrams 160-Lead Plastic Quad Flatpack N160 2-32 Package Diagrams 160-Lead Ceramic Quad Flatpack (Cavity Up) U162

A144-7S

Abstract: a148-sk
Contextual Info: A144-7S YAGI ANTENNA 144-146 MHZ rusheraft C O R P O R A T I O N 951429 8/93 WARNING THIS ANTENNA IS AN ELECTRICAL CONDUCTOR CONTACT W ITH POWER LINES CAN RESULT IN DEATH OR SERIOUS INJURY DO NOT INSTALL THIS ANTENNA WHERE THERE IS ANY POSSIBILITY OF CONTACT W ITH OR HIGH VOLTAGE ARCOVER FROM POWER CABLES OR SERVICE OROPS TO BUILDINGS. THE ANTENNA. SUPPORTING MAST AND.OR TOWER

n20s

Abstract: A144 BG256 IEEE1164 Military Plastic pASIC 3 Family 256
Contextual Info: 3T PRELIMINARY CYPRESS Ultra38007 UltraLogic Very High Speed 7K Gate CMOS FPGA Features — Minimum Iol and Ioh 24 mA Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

AAAG 6 pin ic

Abstract: n208
Contextual Info: CYPRESS Features PRELIMINARY UltraLogic Very High Speed 7K Gate CMOS FPGA — Minimum Iol and Ioh ° f 24 mA • Flexible logic cell architecture — Wide fan-in up to 16 input gates — Multiple outputs in each cell — Very low cell propagation delay

U208

Abstract: A144 CY7C386P CY7C387P CY7C388P G223
Contextual Info: CY7C387P CY7C388P CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns • Unparalleled FPGA performance for counters, data path, state machines,

Contextual Info: CY7C387A CY7C388A ¿r C Y P R E S S Very High Speed 8K 24K Gate CMOS FPGA Features — 16-bit counter operating at 100 MHz consumes 50 mA — Minimum Iql of 12 mA and Iqh of 8 mA • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies

Contextual Info: CY7C3385A CY7C3386A CYPRESS Features • Very high speed — Loadable counter frequencies greater than SO MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithmetic, and random logic

hp 6263

Abstract: pasic380 CY7C382P CY7C384A CY7C385P CY7C385P-1AC CY7C385P-2AI CY7C386P CY7C388P CERAMIC leaded CHIP CARRIER CLCC 68
Contextual Info: « F CY7C385P CY7C386P C YPR ESS UltraLogic Very High Speed 4K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays

Contextual Info: CY7C387P CY7C388P UltraLogic Very High Speed 8K Gate CMOS FPGA ^ CYPRESS Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns

transistor A144

Abstract: CY7C056V CY7C057V
Contextual Info: 1 CY7C056V CY7C057V PRELIMINARY 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM • Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device • On-Chip arbitration logic • Semaphores included to permit software handshaking

TQFP 144 PACKAGE

Abstract: transistor A144 A101 TQFP 32 PACKAGE a101 transistor TQFP Package 44 lead A101 Package A144 transistor data sheet A64 Package pdf A101 datasheet
Contextual Info: Package Diagram Thin Quad Flat Packs 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 1 Package Diagram 44-Lead Thin Plastic Quad Flat Pack A44 64-Pin Thin Quad Flat Pack A64 2 Package Diagram 64-Lead Thin Plastic Quad Flat Pack A65 3 Package Diagram 80-Pin Thin Plastic Quad Flat Pack A80

n20s

Abstract: pasic380 A144 CY7C3386A CY7C3387P CY7C3388P
Contextual Info: PRELIMINARY 5f CYPRESS Features • Very high speed — Loadable counter frequencies greater than 80 MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines, arithm etic, and random logic

A101

Abstract: A144
Contextual Info: Package Diagrams Thin Quad Flat Packs 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 51-85063-B 44-Lead Thin Plastic Quad Flat Pack A44 51-85064-B 1 Package Diagrams 64-Pin Thin Plastic Quad Flat Pack 10 x 10 x 1.4 mm A64 51-85051-A 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65

FPGA 144 CPGA 172 PLCC ASIC

Abstract: A144 CY7C386A CY7C387A CY7C387A-2GC CY7C388A CY7C387A2AI
Contextual Info: CY7C387A CY7C388A PRELIMINARY CYPRESS Very High Speed 8K 24K Gate CMOS FPGA Features — 16-bit counter operating at 100 MHz consumes 50 mA — Minimum I o l of 12 mA and Ioh °f • Very high speed — Loadable counter frequencies greater than 100 MHz — Chip-to-chip operating frequencies

Contextual Info: CY7C385A CY7C386A i f CYPRESS Very High Speed 4K 12K Gate CMOS FPGA — Fast, fully automatic place and route — Waveform simulation with back an­ notated net delays — PC and workstation platforms Robust routing resources — Fully automatic place and route of

kt 84l

Contextual Info: CY7C385P CY7C386P » r CYPR ESS UltraLogic Very High Speed 4K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies up to 110 MHz — Input + logic cell + output delays under 6 ns

bU1011

Abstract: 026R ca2dc CY7C09569V
Contextual Info: CY7C09569V CY7C09579V PREUM INAm 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM 3.3V Low operating power Features • True Dual-Ported mem ory cells which allow sim ulta­ neous access of the same mem ory location • 2 Flow-Through/Pipelined devices

CM4081

Abstract: CY7C385A-1AI CY7C385A CY7C386A
Contextual Info: CY7C385A CY7C386A CYPRESS Very High Speed 4K 12K Gate CMOS FPGA — Fast, fully automatic place and route — Waveform simulation with back an­ notated net delays — PC and workstation platforms Robust routing resources — Fully automatic place and route of

A48A

Abstract: A101 120-PIN 7x7x1.4 160-PIN plastic quad flat pack 10X10X1.4 tqfp 44
Contextual Info: Package Diagrams Thin Quad Flat Packs 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 51-85063-B 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B 1 Package Diagrams 44-Lead Thin Plastic Quad Flat Pack A44 51-85064-B 44-Lead Thin Plastic Quad Flat Pack 10 x 10 x 1.0 mm A44SB

Contextual Info: V CYPRESS CY7C056V CY7C057V PRELIMINARY 3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM Features True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location 16K x 36 organization CY7C056V 32K x 36 organization (CY7C057V)

CY7C09569V

Abstract: CY7C09579V
Contextual Info: # CYPRESS CY7C09569V PRELIMINARY _ CY7C09579V 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM 3.3V Low operating power Features • True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location • Two Flow-Through/Pipelined devices

transistor A144

Abstract: A144 transistor data sheet CY7C09569V CY7C09579V
Contextual Info: 25/0251 CY7C09569V CY7C09579V 3.3V 16K/32K x 36 FLEx36 Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices — 16K x 36 organization CY7C09569V

CY7C3382A

Abstract: CY7C3384A CY7C3385A CY7C3386A
Contextual Info: CY7C3385A CY7C3386A CYPRESS UltraLogic 3.3V High Speed 4K Gate CMOS FPGA Features • Very high speed — Loadable counter frequencies greater than 80 MHz — Chip-to-chip operating frequencies up to 60 MHz • Unparalleled FPGA performance for counters, data path, state machines,