A020209 Search Results
A020209 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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HV9708
Abstract: A020209
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hv9708a020209 | |
SIVPContextual Info: VP0109 P-Channel Enhancement-Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► The Supertex VP0109 is an enhancement-mode normallyoff transistor that utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing |
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vp0109dsfp-vp0109a020209sivp | |
sivn
Abstract: VN0550 VN0550N3-G 125OC
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vn0550dsfp-vn0550a020209sivn+2 | |
sivn fet
Abstract: sivn
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vn1206dsfp-vn1206a020209sivn fet+1 | |
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Contextual Info: HV7022 Die Specification Pad Layout 12 0,0 13 14 15 16 17 18 19 20 21 22 23 11 24 10 25 9 26 8 27 7 28 6 29 5 30 4 31 3 32 2 33 1 34 43 42 41 40 39 38 37 36 35 Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 185 155 |
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hv7022hv7022ca020209 | |
HV9808Contextual Info: HV9808 Die Specification Pad Layout 12 14 13 16 17 18 19 20 21 22 23 11 24 10 25 9 26 8 27 7 28 6 29 5 30 4 31 3 32 2 0,0 15 42 41 40 39 1 38 37 36 35 33 34 Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 113 97 20 ± 1.0 |
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hv9808a020209 | |
HV57908Contextual Info: HV57908 Die Specification Pad Layout 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 0,0 23 42 22 43 21 44 20 45 19 46 18 47 17 48 16 49 15 50 14 51 13 52 12 53 11 54 10 55 9 56 8 57 7 58 6 59 5 60 4 61 3 62 2 63 1 64 65 80 79 78 77 76 75 74 73 72 |
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hv57908a020209 | |
HV7620Contextual Info: HV7620 Die Specification Pad Layout 22 0,0 23 25 24 21 26 20 27 19 28 18 29 17 30 16 31 15 32 14 33 13 34 12 35 11 36 10 37 9 38 8 39 7 40 6 41 5 42 4 3 2 43 44 45 1 46 64/63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 Die Specifications Die Dimensions |
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hv7620408-222-88plicationsa020209 | |
sivnContextual Info: VN3515 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description This enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities |
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vn3515dsfp-vn3515a020209sivn | |
sivp VP0104
Abstract: SIVP vp0104
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vp0104dsfp-vp0104a020209sivp vp0104+1 | |
sivnContextual Info: VN0808 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► This enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination |
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vn0808dsfp-vn0808a020209sivn | |
sivn
Abstract: sivn fet VN0104N3-G marking n3 VN0104 sivn transistor DSPD-3TO92N3
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vn0104dsfp-vn0104a020209sivn+5 | |
sivn
Abstract: sivn fet 125OC VN3515 3515L
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vn3515dsfp-vn3515a020209sivn+3 | |
sivn
Abstract: sivn fet vn0106 SIVN01 marking n3 VN0106N3-G
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vn0106dsfp-vn0106a020209sivn+4 | |
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Contextual Info: VN2410 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► This enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination |
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vn2410dsfp-vn2410a020209 | |
sivnContextual Info: VN0606 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► This enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination |
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vn0606dsfp-vn0606a020209sivn | |