A 512 J Search Results

A01 monolithic amplifier

Abstract: A02 monolithic amplifier CCD LINEAR SENSOR 512 CCD linear array A03 monolithic amplifier CCD412A Loral linear image sensor transparent substrate Contact image sensor fairchild
Contextual Info: LDRAL Fairchild Im aging Sensors C C D 4 1 2 A 512 x 512 Element Full Frame Image SenSOf FEATURES • 512 x 512 Photosite Array ■ 1£^m x 1£pim Pixel ■ 7.68mm x 7.68 mm Image Area ■ 100% Fill Factor ■ Multi-Pinned Phase MPP Option ■ Readout Noise Less Than 7 Electrons at 250k pixels/ sec

vdfpn8

Abstract: AN1995 M25P05-A
Contextual Info: M25P05-A 512 Kbit, serial Flash memory, 50 MHz SPI bus interface Features • 512 Kbit of Flash memory ■ Page Program up to 256 bytes in 1.4 ms (typical) ■ Sector Erase (256 Kbit) in 0.65 s (typical) ■ Bulk Erase (512 Kbit) in 0.85 s (typical) ■

Contextual Info: R XCR3512XL: 512 Macrocell CPLD DS081 v1.8 January 5, 2005 14 Product Specification Features Description • • • • • The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide

Contextual Info: CY62148EV30LL Automotive 4-Mbit 512 K x 8 Static RAM 4-Mbit (512 K × 8) Static RAM Features Functional Description • Very high speed: 55 ns ❐ Wide voltage range: 2.20 V to 3.60 V The CY62148EV30LL Automotive is a high performance CMOS static RAM organized as 512 K words by 8 bits. This device

DA10

Abstract: DA16 DB10 IDT72511 IDT72521
Contextual Info: IDT72511 IDT72521 Parallel Bidirectional FIFO 512 x 18 & 1,024 x 18 FEATURES: DESCRIPTION: Two side-by-side FIFO memory arrays for bidirectional data transfers ♦ 512 x 18-Bit - 512 x 18-Bit IDT72511 ♦ 1,024 x 18-Bit - 1,024 x 18-Bit (IDT72521) ♦ 18-bit data buses on Port A side and Port B side

AN56

Abstract: X20C04 X20C05 X20C16
Contextual Info: APPLICATION NOTE A V A I L A B L E AN56 X20C05 X20C05 4K 512 x 8 High Speed AUTOSTORE NOVRAM FEATURES DESCRIPTION • • The Xicor X20C05 is a 512 x 8 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM E2PROM . The

Contextual Info: R XCR3512XL: 512 Macrocell CPLD DS081 v1.6 September 23, 2003 14 Product Specification Features Description • • • • • The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide

Contextual Info: CY7C1049CV33 Automotive 4-Mbit 512 K x 8 Static RAM 4-Mbit (512 K × 8) Static RAM Features Functional Description • Temperature ranges ❐ Automotive -A: –40 °C to 85 °C ❐ Automotive-E: –40 °C to 125 °C The CY7C1049CV33 Automotive is a high performance CMOS

Contextual Info: HM62V8512B Series 4 M SRAM 512-kword x 8-bit HITACHI ADE-203-905C (Z) Rev. 2.0 Jan. 29, 1999 Description The Hitachi HM62V8512B is a 4-Mbit static RAM organized 512-kword x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 (J,m Hi-CMOS process technology.

AM7201

Abstract: AM7201-25 AM7201-35 AM7201-50 PDW028 10175G-11
Contextual Info: a Am7201 Advanced Micro Devices High Density First-In First-Out FIFO 512 x 9-Bit CMOS Memory DISTINCTIVE CHARACTERISTICS Status flags—full, half-full, empty • ■ RAM based FIFO 512 x ^organization ■ Cycle times of 35/45/65 ns for standard products

CY7C1049CV33-8ZSXC

Contextual Info: CY7C1049CV33 4-Mbit 512 K x 8 Static RAM 4-Mbit (512 K × 8) Static RAM Features Functional Description • Temperature ranges ❐ Commercial: 0 °C to 70 °C The CY7C1049CV33 is a high performance Complementary metal oxide semiconductor (CMOS) Static RAM organized as

D2911

Abstract: bit-slice
Contextual Info: TMS2150A 512 x 8 CACHE ADDRESS COMPARATOR D2911, M A RCH 1 982-R E V IS E D SEP TE M B E R 1990 DW, JD, OR NT PACKAGE TOP VIEW ’ACT2150A is Recommended for New Designs RESET[ 1 U Fast Address to Match Valid Delay - Two Speed Ranges: 35 ns and 45 ns 512

Contextual Info: Œ \ H A R R HM-6642/883 IS S E M I C O N D U C T O R 512 January 1992 X 8 CMOS PROM Features Description • This Circuit Is Processed In Accordance to Mil-Std883 and Is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link

Contextual Info: CY7C1062DV33 16-Mbit 512 K x 32 Static RAM 16-Mbit (512 K × 32) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1062DV33 is a high performance CMOS Static RAM organized as 524,288 words by 32 bits. ■ Low active power

Contextual Info: CY7C1062DV33 16-Mbit 512 K x 32 Static RAM 16-Mbit (512 K × 32) Static RAM Features Functional Description • High speed ❐ tAA = 10 ns The CY7C1062DV33 is a high performance CMOS Static RAM organized as 524,288 words by 32 bits. ■ Low active power

8Mx4X16

Abstract: sodimm pinout
Contextual Info: 64MX 64 UNBUFFERED SDRAM SODIMM SDRAM SODIMM MODULE 512 MByte 64M x 64 SDRAM Unbuffered 144 Pin SODIMM LOW PROFILE (1.03 inch height) General Description: This memory module is a high performance 512 Megabyte Unbuffered synchronous dynamic RAM module organized as 64M x 64 in a 144 pin Small Outline Dual In-Line Memory Module

SN74ACT7804

Abstract: SN74ACT7806 SN74ACT7814 LG5C 20G22
Contextual Info: SN74ACT7804 512 x 18 FIRST-IN, FIRST-OUT MEMORY SCAS204 -A P R IL 1992 DL PACKAGE TOP VIEW • Member of the Texas Instruments Widebus ,M Family • Load Clock and Unload Clock Can Be Asynchronous or Coincident RESET[ 1 D17 [ 2 • 512 Words by 18 Bits u

SN74ACT7804

Abstract: SN74ACT7806 SN74ACT7814
Contextual Info: SN74ACT7804 512 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY S C AS 204C - APRI L 1992 - REVISED A P R IL 1998 Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 512 Words by 18 Bits Low-Power Advanced CMOS Technology

TH58512FT

Contextual Info: TOSHIBA TH58512FT TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT TENTATIVE 512-MBIT 64M X SILICON GATE CMOS 8 BITS CMOS NAND E2PROM DESCRIPTION The TH58512 is a single 3.3-V 512-Mbit (553,648,128) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes X 32 pages X 4096 blocks.

HM628512BI

Abstract: HM628512BLFPI-7 HM628512BLFPI-8 HM628512BLPI-7 HM628512BLPI-8 HM628512BLRRI-7 HM628512BLRRI-8 HM628512BLTTI-7 HM628512BLTTI-8 Hitachi DSA00358
Contextual Info: HM628512BI Series 4 M SRAM 512-kword x 8-bit ADE-203-935C (Z) Rev. 2.0 Aug. 24, 1999 Description The Hitachi HM628512BI is a 4-Mbit static RAM organized 512-kword × 8-bit. HM628512BI Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process

R1RW0408D

Abstract: R1RW0408DGE-2LR R1RW0408DGE-2PR
Contextual Info: R1RW0408D Series 4M High Speed SRAM 512-kword x 8-bit REJ03C0111-0100Z Rev. 1.00 Mar.12.2004 Description The R1RW0408D is a 4-Mbit high speed static RAM organized 512-kword × 8-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS501-00016-3v0-E Memory FRAM 4 K 512 x 8 Bit I2C MB85RC04V • DESCRIPTION The MB85RC04V is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 512 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the

NE502N

Abstract: NE502-N NE502
Contextual Info: NE502-N DESCRIPTION APPLICATIONS The NE502 is a MOS monolithic integrated circuit, generally intended to delay ana­ logue signals e.g. delay tim e = 512/2fo . • • • • • • It can be used with clock frequencies in the range 5kHz to 500kHz. The device contains 512 stages, so the input

HM628512B

Abstract: HM628512BLFP-5 HM628512BLFP-5SL HM628512BLFP-7 HM628512BLFP-7SL HM628512BLP-5 HM628512BLP-5SL HM628512BLP-7 HM628512BLP-7SL Hitachi DSA00197
Contextual Info: HM628512B Series 4 M SRAM 512-kword x 8-bit ADE-203-903 (Z) Preliminary Rev. 0.0 Apr. 24, 1998 Description The Hitachi HM628512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The