T7201A Search Results

T7201A-MC

Contextual Info: Preliminary Data Sheet M icroelectronics T7201A Multi-Port Repeater Unit MPR2 Features Description • Functionally compatible with IEEE 802.3, Section 9, specification* The T7201A Multi-Port Repeater Unit (MPR2) is a VLSI device that simplifies the design and

twido

Abstract: T7200
Contextual Info: at&t Preliminary Data Sheet M icroelectronics T7201A Multi-Port Repeater Unit MPR2 Features Description • Functionally compatible with IEEE 802.3, Section 9, specification* The T7201A Multi-Port Repeater Unit (MPR2) is a VLSI device that simplifies the design and

Contextual Info: T7201A-25, T7201A-35, T7201A-50 512 x 9 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY D3101. MARCH 1988 • Asynchronous Operation S N 74A C T72 01A . . . N PACKAGE TOP VIEW • Lower Power Consumption Active . . . 400 mW Power Down . . . 3 mW

K9686-B

Contextual Info: PreliminaryData Sheet February1992 ; s AT&T '^^^’Microelectronics T7240A Twisted-Pair Port Transceiver TPORT2 Issue 1.0 Features Description • Compliance with IEEE Std. 802.3M 990 10BASE-T standard The T7240A Twisted-Pair Port Transceiver (TPORT2) simplifies the design and implementation of one

transformer EC-28

Abstract: t7240a 0921e 7495 dip switch pin diagram of ic 7495 TWISTED PAIR WIRE PE65263 T7240A-EC T7240A-PC PE32101
Contextual Info: MAR 2 r Yi-u Preliminary Data Sheet February 1992 ; ^ AT&T M icroelectronics T7240A Twisted-Pair Port Transceiver TPORT2 Issue 1.0 Features Description • Compliance with IEEE Std. 802.3M 990 10BASE-T standard The T7240A Tw isted-P air Port T ransceiver (TPORT2)

KM75C01

Abstract: amd 638 pin 0E17
Contextual Info: CMOS FIFO KM75C01A First-in First-out FIFO 5 1 2 x 9 CMOS M em ory FEATURES DESCRIPTION • First-in, F irst-o ut dual p o rt m em ory — 512 x 9 organization • Very high speed independent o f d e p th /w id th — 25ns cycle tim es • Asynchronous and sim ultaneous read and w rite

K93C46

Abstract: 93cs46n MB832001 hn62308 41C1000 93C46LN 41464 hn623257 HM63832 DT71256
Contextual Info: MEMORY ICs CROSS REFERENCE GUIDE 3. CROSS REFERENCE GUIDE 3.1 DRAM D ensity 256K X 1 F. P a g e KM 41C 256 TC 51256 X 1 X 4 4M X 1 X 4 , 1 6M To sh iba M od e X 4 1M Sam su ng Org. H ita ch i Fu jitsu HM 51256 M B81256 NEC /iP D 4 1 2 5 6 N ib b le KM 41C 257

KM75C01

Contextual Info: KM75C01A CMOS FIFO First-in First-out FIFO 5 1 2 x 9 CMOS Memory FEATURES DESCRIPTION • First-in, First-out dual port memory — 512 x 9 organization • Very high speed independent of depth/width 25ns cycle times • Asynchronous and simultaneous read and write