STP210 Search Results

Contextual Info: P200 -18/Ud STP210 - 18/Ud STP190 - 18/Ud 210 Watt Maximum Power SOLAR PANEL Features • High conversion efficiency based on leading innovative photovoltaic technologies • High reliability with guaranteed +/-3% power output tolerance, ensuring return on investment

stp210n75

Abstract: STP210N75F6 210N75F6
Contextual Info: STP210N75F6 N-channel 75 V, 3 mΩ, 120 A TO-220 STripFET VI DeepGATE™ Power MOSFET Features Order code VDSS RDS on max ID STP210N75F6 75 V < 3.7 mΩ 120 A • Low gate charge ■ Very low on-resistance ■ High avalanche ruggedness 3 1 2 TO-220 Application

schematic diagram reverse forward motor

Abstract: STB210NF02 STB210NF02-1 STB210NF02T4 STP210NF02
Contextual Info: STP210NF02 STB210NF02 STB210NF02-1 N-CHANNEL 20V - 0.0026 Ω - 120A D²PAK/I²PAK/TO-220 STripFET II POWER MOSFET AUTOMOTIVE SPECIFIC TYPE STB210NF02/-1 STP210NF02 • ■ ■ VDSS RDS on ID 20 V 20 V <0.0032 Ω <0.0032 Ω 120 A(*) 120 A(*) TYPICAL RDS(on) = 0.0026Ω

STB210NF02

Abstract: STB210NF02-1 STB210NF02T4 STP210NF02 p210n B210NF02
Contextual Info: STP210NF02 STB210NF02 STB210NF02-1 N-CHANNEL 20V - 0.0026 Ω - 120A D²PAK/I²PAK/TO-220 STripFET II POWER MOSFET AUTOMOTIVE SPECIFIC TYPE STB210NF02/-1 STP210NF02 • ■ ■ VDSS RDS on ID 20 V 20 V <0.0032 Ω <0.0032 Ω 120 A(*) 120 A(*) TYPICAL RDS(on) = 0.0026Ω

STB210NF02

Abstract: STB210NF02-1 STB210NF02T4 STP210NF02
Contextual Info: STP210NF02 STB210NF02 STB210NF02-1 N-CHANNEL 20V - 0.0026 Ω - 120A D2PAK/I2PAK/TO-220 STripFET II POWER MOSFET AUTOMOTIVE SPECIFIC • ■ ■ TYPE VDSS R DS on ID PD STB210NF02/-1 STP210NF02 20 V 20 V <0.0032 Ω <0.0032 Ω 120 A 120 A 300 W 300 W

Contextual Info: STP210NF02 STB210NF02 STB210NF02-1 N-CHANNEL 20V - 0.0026 Ω - 120A D PAK/I PAK/TO-220 STripFET II POWER MOSFET AUTOMOTIVE SPECIFIC TYPE V DSS R DS on ID 20 V 20 V <0.0032 Ω <0.0032 Ω 120 A(*) 120 A(*) STB210NF02/-1 STP210NF02 • ■ ■ TYPICAL RDS(on) = 0.0026Ω

STP2014

Abstract: MK48T08-1 EBA11 STP2104 AmZ8 AD27 AD29 AD30
Contextual Info: STP2014.frm 1 Mon Jul 7 08:25:34 1997 STP2014 July 1997 SEC DATA SHEET SBus-to-EBus Controller DESCRIPTION The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the interrupt control and steering logic, the timer/counter registers, reset logic, and miscellaneous registers. The

TAZ BI-DIR

Abstract: Mbus master 250 slave circuit STP2103 MAD32
Contextual Info: S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive inter­

Contextual Info: STP2014 S un M ic r o e l e c t r o n ic s July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter­

STP2013

Abstract: Mbus master 250 slave circuit STP2013PGA-50 m-bus mbus STP2011 STP2013PGA50 MAD44
Contextual Info: STP2013PGA-50 July 1997 EMC DATA SHEET Error-Correcting Memory Controller DESCRIPTION The STP2013 Error-Correcting Memory Controller control mechanism consists of a central arbiter that selects between MBus and graphics-request masters, while monitoring periodic refresh and VIO preemptive interrupts. Satellite state machines are granted execution by the arbiter in response to a buffered request. Stalled

Contextual Info: S T P 2 Û1 3 P G A -50 S un M ic r o e le c t r o n ic s July 1997 EMC DATA SHEET Error-Correcting M emory Controller D e s c r ip t io n The STP2013 Error-C orrecting M em ory C ontroller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request m asters, w hile m onitoring periodic refresh and VIO preem ptive inter­

D37M

Contextual Info: STP2013PGA-50 S un M ic r o e l e c t r o n ic s J u ly 1997 EMC DATA SHEET Error-Correcting Memory Controller D e s c r ip t io n The STP2013 Error-Correcting M em ory Controller control m echanism consists of a central arbiter that selects betw een M Bus and graphics-request masters, while m onitoring periodic refresh and VIO preem ptive inter­

STP2014QFP

Contextual Info: STP2014.frm 1 Mon Jul 7 08:25:34 1997 S un M e ic r o e l e c t r o n ic s J u ly 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/m ouse. The STP2014 also houses the inter­

E-BA8

Abstract: ISOS refer STP2104
Contextual Info: S un M ic ro electro nics July 1997 SEC DATA SHEET SBus-to-EBus Controller D e s c r ip t io n The STP2014 SBus-to-EBus Controller SEC is an interface between the SBus and the EBus that is used for slow I/O devices such as TOD, EPROM, serial port, and keyboard/mouse. The STP2014 also houses the inter­