SN74S260 Search Results

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2006 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN54S260J ACTIVE CDIP J 14 1 TBD A42 SNPB SN74S260D ACTIVE SOIC D

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN54S260J ACTIVE CDIP J 14 1 TBD A42 SN74S260D ACTIVE SOIC D 14 50

SN74S260N

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN54S260J ACTIVE CDIP J 14 1 TBD Call TI SN74S260D ACTIVE SOIC D

Contextual Info: SN54S260, SN74S260 DUAL 5-INPUT POSITIVE-NOR GATES DECEMBER 1 9 8 3 - REVISED M AR C H 1 9 8 8 SN5 4 8 2 6 0 . . . J OR W PACKAGE SN 74S 260 . . . D OR N PACKAGE • Package Options Include Ceramic Chip Carriers and Flat Packages in Addition to Plastic and Ceramic DIPs

Contextual Info: SN54S260, SN74S260 DUAL 5-INPUT POSITIVE-NOR GATES DECEMBER 1983 - REVISED MARCH 1988 S N 5 4 8 2 6 0 . . . J OR W PACKAGE S N 74S 260 . . . D OR N PACKAGE Package Options Include Ceramic Chip Carriers and Flat Packages in Addition to Plastic and Ceramic DIPs

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN54S260J ACTIVE CDIP J 14 1 TBD A42 SNPB SN74S260D ACTIVE SOIC D

diagram CD 5265 cs

Contextual Info: TYPES SN54S260, SN74S260 DUAL 5-INPUT POSITIVE -NOR GATES REVISED DECEM BER 1983 SN 54S260 I OR W PACKAGE SN 74S260 . . . D, J OR N PACKAGE Package Options Include Both Plastic and Ceram ic Chip Carriers in Addition to Plastic and Ceram ic DIPs {TOP VIEW

SN54S260

Abstract: SN74 SN74S260 752B5
Contextual Info: SN54S2GQ, SN74S260 DUAL 5-INPUT POSITIVENOR GATES SDLS208 DECEMBER 1 9 8 3 - SN 548Z60 Package Options Include Ceramic Chip Carriers and Flat Packages in Addition to Plastic and Ceramic DIPs . . J OR W P A C K A G E S N 7 4 S 2 6 0 . . . D OR N P A C K A G E

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN54S260J ACTIVE CDIP J 14 1 TBD A42 SN74S260D ACTIVE SOIC D 14 50

SN54S260J

Abstract: SN74S260D SN74S260DE4 SN74S260DR SN74S260DRE4 SN74S260N SN74S260N3 SN74S260NE4 SNJ54S260FK SNJ54S260J
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN54S260J ACTIVE CDIP J 14 1 TBD Call TI SN74S260D ACTIVE SOIC D

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN54S260J ACTIVE CDIP J 14 1 TBD A42 SNPB SN74S260D ACTIVE SOIC D

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN54S260J ACTIVE CDIP J 14 1 TBD A42 SN74S260D ACTIVE SOIC D 14 50

hct 4047 bt

Abstract: SN74ALS679 FCT Fast CMOS TTL Logic 74LS 4075 7804 inverter SN74368A DTL Logic 4069 CMOS hex inverter SN502 CD74AC374
Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

74HCT 4013

Abstract: CD4078 4093 BF SN74368A SN74ALS679 LXZ Series 4069 CMOS hex inverter 2a2 vacuum tube CD74AC374 cd408
Contextual Info: SN54HC240, SN74HC240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS128B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HC240 . . . J OR W PACKAGE SN74HC240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

Contextual Info: IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

SN54S260

Abstract: SN74S260
Contextual Info: SN S 4S 26 0 , S N 74 S 2 6 0 D U A L 5-IN PU T P O S IT IV E-N O R G A T E S DECEMBER 1983 - {TO P V IE W C1 U 1BC 2 1CC 3 Dependable Texas Instruments Quality and Reliability ia These devices contain tw o independent 5-input positive gates. They perform

SN74ALVCH162245

Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
Contextual Info: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

FT 4013 d dual flip flop

Abstract: FT 4013 D flip flop 74HC octal bidirectional latch 74HCT 4013 DATASHEET 4511 pin configuration SN7432 fairchild CMOS TTL Logic Family Specifications 7805 acv Datasheet of decade counter CD 4017 sn74154
Contextual Info: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX

LG color tv Circuit Diagram schematics

Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
Contextual Info: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS

sn74 series TTL logic gates list

Abstract: IC 4073 SCLS298 SN74LS02 function SN74368A electromechanical catalog Tubes Catalog 4066 bd for sn74ls04 SDFD001B
Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

CD4000 SERIES BOOK

Abstract: ten segment display 74HC nobel tv circuit SCLS298 SN74BCT126 8Q 4030 DECADE COUNTER 4017 PIN OUT DIAGRAM WORKING IC 4026 CMOS DECADE COUNTER 4017 Difference between LS, HC, HCT, H
Contextual Info: SN54ALS373, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083B – APRIL 1982 – REVISED DECEMBER 1994 OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND These octal transparent D-type latches feature 3-state outputs designed specifically for driving

SN502

Abstract: 74HCT 4013 SN74368A ic 4024 7-stage counter 163245 cd408 CD74AC374 1A2 CPU TSSOP 20PIN sn7414 circuit 4000 series CMOS Logic ICs 4030
Contextual Info: SN54F244, SN74F244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SDFS063A – D2932, MARCH 1987 – REVISED OCTOBER 1993 • SN54F244 . . . J PACKAGE SN74F244 . . . DB, DW, OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN54S260J ACTIVE CDIP J 14