SN74LS24 Search Results

741t

Abstract: L076
Contextual Info: TYPES SNS4LS242, SN54LS243, SN74LS242. SN74LS243 QUADRUPLE BUS TRANSCEIVERS • Two-Way Asynchronous Communication Between Data Bums • P-N-P Inputs Reduce D-C Loading • Hysteresis Typically 400 mV at Inputs Improves Noise Margin 8N64LS242 . . . J O R W

Contextual Info: SN54LS242, SN54LS243, SN74LS242, SN74LS243 QUADRUPLE BUS TRANSCEIVERS APHIL 1985 —REVISED MARCH 198B • T w o -W a y Asynchronous C om m unication B etw een D ata Buses • P N P Inputs Reduce D -C Loading SN 54LS 242, SN 54LS 243 . . . J OR W PACKAGE SN 74LS 242. SN 74LS243 . . . D OR N PACKAGE

pin diagram of SN74LS244N

Contextual Info: SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDLS144C − APRIL 1985 − REVISED MAY 2010 Memory Address Registers D PNP Inputs Reduce DC Loading

Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

datasheet 74LS241

Abstract: LS244 SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240 SN74LS241
Contextual Info: SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002 D D 3-State Outputs Drive Bus Lines or Buffer

SN74S241

Abstract: ls244 SN74LS SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN74LS240 SN74LS241
Contextual Info: TYPES SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241 SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241 SN74S244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS S N 5 4 L S '. S N 5 4 S ' . . . J P A C K A G E • 3-State O utputs Drive Bus Lines or Buffer

Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

SN74LS18

Abstract: mini inverter circuit schematic diagram SN74LS SN74LS19 74LS24 Bi 3101 A LS132 LS13 1B57
Contextual Info: TYPES SN74LS18, SN74LS19, SN74LS24 SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS J A N U A R Y • • Functionally and Mechanically Identical

LOGIC sn74LS244n

Contextual Info: SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDLS144C − APRIL 1985 − REVISED MAY 2010 Memory Address Registers D PNP Inputs Reduce DC Loading

74LS240

Abstract: LS240 LS244 SN74LS240 SN74LS240DW SN74LS240DWR2 SN74LS240M SN74LS240N SN74LS244 74LS24x
Contextual Info: SN74LS240, SN74LS244 Octal Buffer/Line Driver with 3-State Outputs The SN74LS240 and SN74LS244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.

Contextual Info: SN54LS243, SN74LS243 www.ti.com . SDLS145A – APRIL 1985 – REVISED JULY 2008 QUADRUPLE BUS TRANSCEIVERS

8002002CA

Contextual Info: SN54LS242, SN54LS243, SN74LS242, SN74LS243 QUADRUPLE BUS TRANSCEIVERS SDLS145 – APRIL 1985 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

LS244

Abstract: JS240 SN74SL SN74SL240 S-244 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244
Contextual Info: SDLS144 SN54LS24G, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244, SN74LS24Q, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS APRIL 1985 —REVISED MARCH 1988 3-State Outputs Drive Bus Lines or Buffer

Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

Contextual Info: SN54LS243, SN74LS243 www.ti.com . SDLS145A – APRIL 1985 – REVISED JULY 2008 QUADRUPLE BUS TRANSCEIVERS

pin diagram of SN74LS244N

Abstract: 244FK SN74LS241N
Contextual Info: SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDLS144C − APRIL 1985 − REVISED MAY 2010 Memory Address Registers D PNP Inputs Reduce DC Loading

LS244

Abstract: SN74LS240 SN74LS244 LS240 SN74LS240DW SN74LS240N SN74LS244DW SN74LS244N
Contextual Info: SN74LS240, SN74LS244 Octal Buffer/Line Driver with 3-State Outputs The SN74LS240 and SN74LS244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.

Contextual Info: SN74LS245 Octal Bus Transceiver The SN74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input DR controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input

Contextual Info: SN54LS243, SN74LS243 www.ti.com . SDLS145A – APRIL 1985 – REVISED JULY 2008 QUADRUPLE BUS TRANSCEIVERS

Contextual Info: SN54LS243, SN74LS243 www.ti.com . SDLS145A – APRIL 1985 – REVISED JULY 2008 QUADRUPLE BUS TRANSCEIVERS

Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins

SN74LS245N

Abstract: 74LS245 LS245 SN74LS245 SN74LS245DW SN74LS245DWR2 SN74LS245M SN74LS245MEL
Contextual Info: SN74LS245 Octal Bus Transceiver The SN74LS245 is an Octal Bus Transmitter/Receiver designed for 8-line asynchronous 2-way data communication between data buses. Direction Input DR controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input

Contextual Info: SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002 D D D D 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins