SN74276 Search Results

AS 15 -g

Abstract: LW2J
Contextual Info: TYPES SN54276, SN74276 QUADRUPLE J-K FLIP-FLOPS O C T O B E R 1 9 7 6 — R E V IS E D D E C E M B E R 1 9 8 3 features • Four J-K Flip-Flops in a Single Package . . . Can Reduce FF Package Count by 50% • Separate Negative-Edge-Triggered Clocks with Hysteresis , . . Typically 200 mV

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2005 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

Contextual Info: SN54276, SN74276 QUADRUPLE J-K FLIP-FLOPS O C T O BER 1976 - R E V IS E D M A R C H 1988 SN 5 42 76 . . . J PA C K A G E • Four J -K Flip-Flops in a Single Package . . Can Reduce F F Package Count by 50% • Separate Negative-Edge-Triggered Clocks with

SN74276N

Abstract: SN74276DW SN74276DWR SN74276N3
Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

7402 J-K Flip-Flop

Abstract: 74276 sn74726
Contextual Info: TTL MSI TYPES SN54276, SN74276 QUADRUPLE J-K FLIP-FLOPS BU LLETIN NO . OL-S 7 6 1 2 4 S 0 , OCTOBER 1 8 7 « SN54Z76. . . J PACKAGE SN7 4 2 7 6 . . . J OR N PACKAGE features • Four J-K Flip-Flops in a Single Package. . . Cm Reduce FF Package Count by 60%

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 7-Jun-2010 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 3-May-2010 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74276DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276N3 OBSOLETE PDIP N 20 TBD Call TI Call TI SN74276N3

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2007 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

Contextual Info: PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status 1 Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74276DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74276DWR OBSOLETE

Contextual Info: SN54276, SN74276 QUADRUPLE J-K FLIP-FLOPS O CTOBER 1976 - SN54276 . . . J PACKAGE SN74276 . . . N PACKAGE TOP VIEW Four J-K Flip-Flops in aSingle Package . . . Can Reduce FF Package Count by 50% Typical Clock Input Frequency . . . 50 MHz • Fully Buffered Outputs

sn74726

Abstract: 74276 SN54276 SN74276 K5S01
Contextual Info: SN54276, S N74276 QUADRUPLE J-K FLIP-FLOPS SDLSQ91 OCTO BER 1 97 6 - • Four J-K Flip-Flops in a Single Package . . , Can Reduce FF Package Count by 50% • Separate Negative-Edge Triggered Clacks with Hysteresis . . . Typically 2 00 m V • Typical Clock Input Frequency . . . 50 MHz

74HCT 4013

Abstract: CD4078 4093 BF SN74368A SN74ALS679 LXZ Series 4069 CMOS hex inverter 2a2 vacuum tube CD74AC374 cd408
Contextual Info: SN54HC240, SN74HC240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS128B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HC240 . . . J OR W PACKAGE SN74HC240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

SN74ALS123

Abstract: SN7401 74LS424 54175 SN74298 SN74265 SN74LS630 SN74LS69 National Semiconductor Linear Data Book Transistor AF 138
Contextual Info: INDEX • FUNCTIONAL SELECTION GUIDE • NUMERICAL FUNCTION INTERCHANGEABILITY GUIDE GENERAL INFORMATION AND EXPLANATION OF NEW LOGIC SYMBOLS ORDERING INSTRUCTIONS AND MECHANICAL DATA 54/74 SERIES OF COMPATIBLE TTL CIRCUITS • PIN OUT DIAGRAMS 54/74 FAMILY SSI CIRCUITS

SN74ALVCH162245

Abstract: Schottky Barrier Diode Bus-Termination Array SN7400 CLOCKED SLLS210 SCAD001D TEXAS INSTRUMENTS SN7400 SERIES buffer SN74LVCC4245 sn74154 SDAD001C SN7497
Contextual Info: Section 4 Logic Selection Guide ABT – Advanced BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 ABTE/ETL – Advanced BiCMOS Technology/ Enhanced Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9

FT 4013 d dual flip flop

Abstract: FT 4013 D flip flop 74HC octal bidirectional latch 74HCT 4013 DATASHEET 4511 pin configuration SN7432 fairchild CMOS TTL Logic Family Specifications 7805 acv Datasheet of decade counter CD 4017 sn74154
Contextual Info: T H E W O R L D L E A D E R I N L O G I C P R O D U C T S Logic Selection Guide February 2000 1999 EEProduct News PRODUCTS OF THE YEAR AWARD New products for prototype design AVC Advanced Very-Low-Voltage CMOS Logic See Section 4 LOGIC OVERVIEW 1 FUNCTIONAL INDEX

LG color tv Circuit Diagram schematics

Abstract: texas ttl YJ 162A Texas Instruments TTL integrated circuits catalog SN74180 AC digital voltmeter using 7107 Sii 9024 MC3123 sn74ls860 SN7490AJ sn74243
Contextual Info: IN D EXES Alphanumeric • Functional/Selection Guide IN T E R C H A N G E A B ILIT Y GUIDE G E N E R A L INFORM ATION O RD ERIN G IN STRUCTIO N S AND M ECH A N ICA L D A TA 5 4 /7 4 FA M ILIE S OF CO M PATIBLE T T L C IR C U ITS 54/74 F A M IL Y SSI C IR C U ITS

sn74 series TTL logic gates list

Abstract: IC 4073 SCLS298 SN74LS02 function SN74368A electromechanical catalog Tubes Catalog 4066 bd for sn74ls04 SDFD001B
Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

CD4000 SERIES BOOK

Abstract: ten segment display 74HC nobel tv circuit SCLS298 SN74BCT126 8Q 4030 DECADE COUNTER 4017 PIN OUT DIAGRAM WORKING IC 4026 CMOS DECADE COUNTER 4017 Difference between LS, HC, HCT, H
Contextual Info: SN54ALS373, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083B – APRIL 1982 – REVISED DECEMBER 1994 OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND These octal transparent D-type latches feature 3-state outputs designed specifically for driving

SN502

Abstract: 74HCT 4013 SN74368A ic 4024 7-stage counter 163245 cd408 CD74AC374 1A2 CPU TSSOP 20PIN sn7414 circuit 4000 series CMOS Logic ICs 4030
Contextual Info: SN54F244, SN74F244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SDFS063A – D2932, MARCH 1987 – REVISED OCTOBER 1993 • SN54F244 . . . J PACKAGE SN74F244 . . . DB, DW, OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

SN7401

Abstract: sn29601 SN7449 SN74298 SN74265 MC3021 SN54367 sn74142 signetics 8223 9370c
Contextual Info: INDEX PAGE TTL Integrated Circuits Mechanical Data 1 TTL Interchangeability Guide 6 Functional Selection Guide 19 Explanation of Function Tables 38 54/74 Families of Compatible TTL Circuits 40 TTL INTEGRATED CIRCUITS MECHANICAL DATA J ceramic dual-in-line package

Contextual Info: ADS7807 AD S 780 7 ADS 780 7 SBAS022C – NOVEMBER 1992 – REVISED FEBRUARY 2006 Low-Power, 16-Bit, Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION ● 35mW max POWER DISSIPATION ● 50µW POWER-DOWN MODE ● 25µs max ACQUISITION AND CONVERSION