SMA100A Search Results

Contextual Info: SMA100A_dat-sw_en_5213-6412-22.indd 1 Data Sheet | 07.00 Test & Measurement R&S SMA100A Signal Generator Specifications 18.10.2013 15:24:48 Version 07.00 October 2013 CONTENTS Key features . 4

Marconi 2030 service manual

Abstract: Marconi 2024 service manual marconi 2030 operating manual
Contextual Info: SMA100A_dat-sw_en_5213-6412-22_cover.indd 1 Data Sheet | 06.01 Test & Measurement R&S SMA100A Signal Generator Specifications 04.06.2013 08:45:04 Version 06.01 June 2013 CONTENTS Key features . 3

DAC1627

Contextual Info: DAC1627D Demo boards – Quick Start v2 1 DAC1627D demoboard+ CGAP2 Board presentation CGAP2 board: Storage and Generation of complex patterns up to 32M I,Q (I Q)- words DAC1627D board 2 DAC1627D demoboard+ CGAP2 Board connections CGAP2 USB Power 5 Vdc SMA100A clock generator : DAC clock

C124 EST

Contextual Info: User's Guide SNAU023A – July 2007 – Revised October 2013 ADC14C105EB and ADC12C105EB Evaluation Boards This User's guide applies to the ADC14C105EB and ADC12C105EB evaluation boards which are used to evaluate the ADC14C105 and ADC12C105 A/D Converters, respectively. These ADCs belong to a family

Contextual Info: Evaluation Board User’s Guide for ADC14V155: 14-Bit, 155 MSPS Analog to Digital Converter with LVDS Outputs N www.national.com Rev 0.3 October 2007 ADC14V155 Evaluation Board User’s Guide Analog Input FIN > 150 MHz Analog Input FIN < 150 MHz Analog Input

atmel 014 24C02

Contextual Info: June 16, 2010 Rev 1.0 National Semiconductor ADC16DV160HFEB Evaluation Board User’s Guide ADC16DV160 Dual 16-Bit, 160 MSPS A/D Converter 2009 National Semiconductor Corporation. 1 http://www.national.com Table of Contents 1.0 Introduction . 3

Contextual Info: 8:1 Differential-to-3.3V or 2.5V LVPECL/ECL Clock Multiplexer ICS853S058I DATASHEET General Description Features The ICS853S058I is an 8:1 Differential-to-3.3V or 2.5V LVPECL / ECL Clock Multiplexer which can operate up to 2.5 GHz. The ICS853S058I has 8 differential selectable clock inputs. The PCLK,

DB01P

Abstract: DCI circuit diagram
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET AD9739 SYNC_OUT SYNC_IN LVDS DDR RECEIVER I120 CLK DISTRIBUTION DIV-BY-4 SYNCCONTROLLER TxDAC CORE IOUTP IOUTN DACCLK 07851-001 DCO VREF DLL (MU CONTROLLER) Broadband communications systems Military jammers Instrumentation, automatic test equipment

ic 11105 circuits diagraM

Abstract: cs 730 C65 004 pin configuration cml T9 LED HSC-ADC-EVALC hsc-adc-evalcz raychem termination jointing instructions AD9627 AD9627-11 AD9627BCPZ11-105
Contextual Info: 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9627-11 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDIO/ SCLK/ DCS DFS CSB FD 0:3 A FD BITS/THRESHOLD DETECT DRVDD SPI PROGRAMMING DATA VIN+A SHA ADC VIN–A SIGNAL MONITOR VREF D10A D0A CLK+ CLK–

d 9329

Abstract: trc 9500 8755 interfacing chip pin diagram of ic 7489 agilent 8762 22253d IC TA 7089 P 74344 IT 8755 E j 5804 f11
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH CLK DISTRIBUTION DIV-BY-4 IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK 09616-001 DB1[13:0] Broadband communications systems DOCSIS CMTS systems

HDR-2X3

Abstract: LP3878MR-ADJ GRM155R71H103KA88D EN56 atmel 130 24c02 ECJ-1VB0J475M ECJ1VB0J475M d2n c60 TAJC106K020R 0201 footprint
Contextual Info: January 9, 2009 Rev 0.9 National Semiconductor Evaluation Board User’s Guide ADC16V130 16-Bit, 130 MSPS A/D Converter 2009 National Semiconductor Corporation. 1 http://www.national.com Table of Contents 1.0 Introduction . 3

Contextual Info: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CDCLVP1208 SCAS890D – OCTOBER 2009 – REVISED SEPTEMBER 2014 CDCLVP1208 Eight LVPECL Output, High-Performance Clock 2:8 Buffer 1 Features 3 Description • • • The CDCLVP1208 is a highly versatile, low additive

Contextual Info: AD9741/3/5/6/7 Evaluation Board Quick Start Guide One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Getting Started with the AD9741/3/5/6/7 Evaluation Board WHAT’S IN THE BOX

Contextual Info: FemtoClock NG Octal Universal Frequency Translator IDT8T49N282I DATA SHEET General Description • The IDT8T49N282I has two independent, fractional-feedback PLLs that can be used as jitter attenuators and frequency translators. It is equipped with six integer and two fractional output dividers, allowing

Contextual Info: FemtoClock Crystal-to-LVDS 8-Output Clock Synthesizer ICS814S208I DATA SHEET General Description Features The ICS814S208I is an eight LVDS output clock synthesizer designed for wireless infrastructure applications. The device generates eight copies of a selectable 122.88MHz or 153.6MHz

Contextual Info: Wideband IF Receiver Subsystem AD6676 Data Sheet FEATURES APPLICATIONS High instantaneous dynamic range Noise figure NF as low as 13 dB Noise spectral density (NSD) as low as −159 dBFS/Hz IIP3 up to 36.9 dBm with spurious tones <−99 dBFS Tunable band-pass Σ-Δ analog-to-digital converter (ADC)

C1518

Abstract: ADC14155 ADC14155HFEB ADC14155LFEB ETC1-1-13 HP8644B NC7WV125K8X SMA100A c7343 footprint
Contextual Info: Evaluation Board User’s Guide for ADC14155: 14-Bit, 155 MSPS Analog to Digital Converter N www.national.com Rev 0.0 September 2007 ADC14155 Evaluation Board User’s Guide Analog Input FIN < 150 MHz Analog Input FIN > 150 MHz Analog Input Network ADC PD

RIGHT ANGLE HEADER CONNECTOR

Abstract: JEDEC MO-187 CA C7343 ADC11C125HFEB ADC11C125LFEB ETC1-1-13 HP8644B NC7WV125K8X SMA100A atmel 24c02
Contextual Info: Evaluation Board User’s Guide for ADC11C125: 11-Bit, 125 MSPS Analog to Digital Converter N www.national.com Rev 0.3 June 2007 ADC11C125 Evaluation Board User’s Guide Analog Input FIN < 150 MHz Analog Input FIN > 150 MHz Analog Input Network ADC PD Jumper

K95 Package

Contextual Info: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMK00804B SNAS642 – JUNE 2014 LMK00804B Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer • 1 • • • • • 3 Description Four LVCMOS/LVTTL Outputs with 7 Ω Output

Contextual Info: Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CDCLVP1208 SCAS890C – OCTOBER 2009 – REVISED JUNE 2014 CDCLVP1208 Eight LVPECL Output, High-Performance Clock 2:8 Buffer 1 Features 3 Description • • • The CDCLVP1208 is a highly versatile, low additive

Contextual Info: LMK00725 www.ti.com SNAS625 – SEPTEMBER 2013 Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer Check for Samples: LMK00725 FEATURES APPLICATIONS • • • • • • • 1 • • • • • • Five 3.3V Differential LVPECL Outputs – Additive Jitter: 43 fs RMS typ @ 312.5

833A tube

Abstract: H-183-4 ICS889833 ICS889833AK MO-220 SMA100A SY89833L
Contextual Info: ICS889833 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION GENERAL DESCRIPTION FEATURES The ICS889833 is a high speed 1-to-4 DifferentialICS to-LVDS Fanout Buffer w/Internal Termination and HiPerClockS is a member of the HiPerClockS™ family of high

Contextual Info: Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL Fanout Buffer ICS853S111BI DATASHEET General Description Features The ICS853S111BI is a low skew, high performance 1-to-10 Differential-to-2.5V/ 3.3V LVPECL/ECL Fanout Buffer. The ICS853S111BI is characterized to operate from either a 2.5V or a

ICS853S058AIL

Abstract: 173-MIL ICS853058 ICS853S058AGI ICS853S058I SMA100A 853S058AGILFT
Contextual Info: 8:1 Differential-to-3.3V or 2.5V LVPECL/ECL Clock Multiplexer ICS853S058I DATASHEET General Description Features The ICS853S058I is an 8:1 Differential-to-3.3V or 2.5V LVPECL / ECL Clock Multiplexer which can operate up HiPerClockS to 2.5 GHz. The ICS853S058I has 8 differential