SCLS189A Search Results

37Ti

Abstract: SN74LV74
Contextual Info: SN74LV74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS189A - FEBRUARY 19 9 3 - REVISED JULY 1995 D, DB, OR PW PACKAGE c ro p VIEW EPIC Enhanced-Performance Implanted CMOS) 2-ii Process Typical V o l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

Contextual Info: SN54HCT74, SN74HCT74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS169A - DECEMBER 1962 - REVISED JANUARY 1996 Inputs Are TTL-Voltage Compatible Package Options Include Plastic Small-Outllne D , Thin Shrink