SCAS680 Search Results
SCAS680 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
32PIN TQFP TEXASContextual Info: SCAS680 CDCLVD110 Q6 Q6 Q5 16 Vdd Q2 26 15 Q7 VCC range 2.5V +/- 5% Q2 27 14 Configurable register SI/CK individually enables / disables outputs and selects between one of two possible input clocks Q1 Q1 28 Q7 Q8 Q9 31 10 Q9 Vdd 32 9 Vss • Full rail-to-rail common-mode input |
Original |
scas680cdclvd110/-100mv32-pin+2 | |
CDC2509Contextual Info: CDC2509 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCASS80-OCTOBER 1996 PW PACKAGE TOP VIEW Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output |
OCR Scan |
cdc2509scass80-october24-pln7526s+1 |