RM5270 Search Results

ACT5270

Abstract: R4700 R5000
Contextual Info: ACT5270 64-Bit Superscaler Microprocessor Features • ■ Full militarized QED RM5270 microprocessor Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle ■ ● Supports ■ ● 133, 150, 200 MHz operating frequencies – Consult Factory for

RM5270

Contextual Info: QED RISCMark RM5270™ 64-Bit Superscalar Microprocessor FEATURES: • • Dual Issue su p e rsca la r m icro p ro ce sso r - can issue one integer and one floa ting -point in stru ction pe r cycle — 150, 200 M Hz opera ting frequ en cies — 260 Dhrystone2.1 M IPS

Contextual Info: — ' I I I I I I I A C T 5270 | M M M — — — — — — — 1— 1— 1— 1— 1— 1— — — — — — — — ' 64-Bit Superscaler Microprocessor Features • Integrated secondary cache controller R5000 compatible ■ Full militarized QED RM5270 microprocessor

qed rm5200

Contextual Info: RM5271 Microprocessor with External Cache Interface Document Rev. 1.3 Date: 02/2000 FEATURES • High-performance floating point unit - up to 700 MFLOPS — Single cycle repeat rate for common single precision operations and some double precision operations

C 5271 manual

Contextual Info: QED RISCMark RM5271™ 64-Bit Superscalar Microprocessor FEATURES: • Dual Issue su p e rsca la r m icro p ro ce sso r - can issue one integer and one floa ting -point in stru ction pe r cycle — 200, 225, 250, 266 M H z op era ting frequ en cies — 345 D hrystone, 2.1 M IP S m axim um

1010 817 g40

Abstract: GT-64111 I960JX
Contextual Info: GT-482xx liiii d | | |G O . GT-48212 / GT-48208 / GT-48207 Prelim inary Revision 1.2 D v 1/27/99 BaseX Please co n ta ct G alileo T echnology fo r possible u p dates b efore fin a lizin g a design. FEATURES • - - • - Provides packet switching functions between

GT-48212

Abstract: TC3001 IC TC3001 "filtering database" GT-48208 GT-64010A GT-64120 Motorola ColdFire 5202 led matrix 16X32 intel 80486 pin diagram
Contextual Info: GT-48212 Advanced Switched Fast Ethernet Controller for 10+10/100 BaseX Preliminary Revision 1.0 March 4, 1998 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES • Single-chip Switched Ethernet Controller for 10 and

GS82032A

Abstract: GS84018A MPC7410 MPC7450 MPC750 MPC755 RM5271 RM7065 intel L2 cache burst length 832KX8
Contextual Info: High Speed Memory Technology for Cache Applications Introduction Many processors today use a high speed cache to accelerate memory access. A level 2 or level 3 cache connected on a backside bus can take advantage of high SRAM bandwidth in providing low latency data access. Today’s performance-oriented applications require

CHE 6100

Contextual Info: QED RISCMark RM7000™ 64-Bit Superscalar Microprocessor Advanced Information FEATURES: • RM 5270 and RM5271 pin com patible • Dual Issue s ym m e tric su p e rsca la r m icro p ro ce sso r w ith in stru c­ tion prefetch op tim ize d for system level p rice/pe rfo rm ance

RM5260

Contextual Info: QED RISCMark RM5260™ 64-Bit Superscalar Microprocessor FEATURES: • Dual Issue su p e rsca la r m icro p ro ce sso r - can issue one integer and one floa ting -point in stru ction pe r cycle — 133, 150, 175 and 200 M Hz opera ting fre q u e n cy — 260 Dhrystone2.1 M IPS

Contextual Info: QED RISCMark RM5271™ 64-Bit Superscalar Advanced Microprocessor Quantum p j Effect Design, Inc. • Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle - 150, 200, 250, 266 MHz operating frequencies

RM7000-263S

Abstract: via 266t R4000 R4650 R4700 R5000 RM5200 RM5271 RM7000 RM7000A
Contextual Info: 03 :2 7: 00 AM RM7000 Microprocessor with On-Chip Secondary Cache Datasheet Released to n Mo nd ay ,0 6J an ua ry ,2 00 3 RM7000 Datasheet Proprietary and Confidential Issue 1, January 2001 Do wn l oa de d by ah m ed m et wa ly of sil ico ne xp er RM7000™ Microprocessor with On-Chip

EV-48004A

Abstract: gt-64011-p GT-32011 GT-64111 DLink ADSL GT-64010A GT-64120 R4640 GT48006A GT-48006-P
Contextual Info: *$/,/ 2 7(&+12/2*< *$ / , / (2 7(&+ 1 2 /2 * < 6+257 250 &$7$/2* 6SULQJ  6<67(0 &21752//(56 IRU 5,6& 352&(66256 6:,7&+(' (7+(51(7 &21752//(56 5(027( $&&(66 &21752//(56 Notices Copyright 1998 Galileo Technology, Inc. All Rights Reserved. GalNet , GalaxyTM, Galileo Technology, Galileo and the Galileo logo are

"filtering database"

Abstract: DP8384Q I960CX IC TC3001 "Spanning Tree" BUT15
Contextual Info: Galileo. GT-48212 Advanced Switched Fast Ethernet Controller for 10+10/100 BaseX Please contact Galileo Technology for possible updates before finalizing a design FEATURES • Single-chip Switched Ethernet Controller for 10 and 1CV100Base-X - Provides packet switching functions between

GT482

Abstract: 48208 GT-48212 Motorola ColdFire 5202 TC3001 diode sy 171 10 4.7kohm resistor GALILEO TECHNOLOGY GT-48208 GT-64010A
Contextual Info: GT-482xx Galileo GT-48212 / GT-48208 / GT-48207 Advanced Switched Ethernet Controllers for 10+10/100 BaseX Preliminary Revision 1.2 1/27/99 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES - Provides packet switching functions between

GT-96100A

Abstract: led matrix 8x64 message circuit ADVANCED COMMUNICATION DEVICES UE401 BV EI 304 2081 MIPS R7000 MIPS R7000 instruction HDLC LAPB 16M x8 55ns 72 pin flash dimm CIRCUIT DIAGRAM UPS
Contextual Info: Galileo GT-96100A Advanced Communication Controller Datasheet Revision 1.0 3 October, 2000 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES • Integrated communication controller and system controller with PCI interface for highperformance embedded control applications.

4M64

Abstract: "Spanning Tree" BUT15
Contextual Info: Galaxy Family Devices lia lile o G T-48212 / G T-48208 / GT-48207 Advanced Switched Ethernet Controllersfor 10+10/100 BaseX for 10OBaseX Please contact Galileo Technology for possible updates before finalizing a design FEATURES • Single-chip Switched Ethernet Controllers for 10 and

QUANTUM CAPACITIVE

Abstract: Quantum Effect Devices GVT7164T18 MCM69T618 R5000 RM5200 RM5271 RM7000 qed rm5200 mips r5000
Contextual Info: External Cache for the RM5271 Application Note Introduction Quantum Effect Devices, Inc. QED was founded in 1991 to design and develop MIPS RISC microprocessors to MIPS Technologies, Inc. (MTI) specifications. MTI sub-licensed those designs to MIPS licensees. In 1996 QED obtained a license

RM5261-250Q

Abstract: MIPS RM5230
Contextual Info: QED RISCMark RM5261™ 64-Bit Superscalar A d vanced Microprocessor Quantum Effect Design, Inc. • Dual Issue superscalar microprocessor - can issue one Integer and one floating-point instruction per cycle - 150, 200, 250,266 MHz operating frequencies

RM5200

Abstract: R4000 MICROPROCESSOR RM7000-263S R4000 R4700 R5000 RM5271 RM7000 Tag 225 600 replacement qed rm5200
Contextual Info: RM7000 Superscalar Dual-Issue Microprocessor with On-Chip L2 Cache FEATURES • Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance — 200, 225, 250, 263, 300 MHz operating frequency — >500 Dhrystone 2.1 MIPS @ 300 MHz

E5403A

Abstract: N4228-68702 E5396-68702 FS1112 LACT 33020 Mictor pinout FS1117 80c165 Rockwell 6502 E5340
Contextual Info: Application Support for Agilent Logic Analyzers Configuration Guide May 1, 2005 Configuring a logic analyzer for your specific application is as easy as one, two, three. To configure a system select the combination of products and capabilities that will Table of Contents

Contextual Info: :4 8: 54 PM RM7000 Microprocessor with On-Chip Secondary Cache Datasheet Released Th ur sd ay ,0 8S ep te m be r, 20 05 12 RM7000 Datasheet Proprietary and Confidential Issue 1, January 2001 Do wn lo ad ed by Co nt e nt Te a m of Pa rtm in er In co n RM7000™ Microprocessor with On-Chip

RM5200

Abstract: MIC29302 footprint 304-SBGA Quantum Effect Devices vero PK100 IPC-D-317B QUANTUM CAPACITIVE LT1085CT LT1584 qed rm5200
Contextual Info: PCB Design Notes for the RM7000 Application Note Introduction The RM7000 is a 64-bit MIPS IV Instruction Set Architecture CPU with 48/64-entry TLB memory management unit, double precision floating point unit, a 64-bit multiplexed address and data bus which is capable of operating at up to 125 MHz .

RM5271

Abstract: RM5200 rm5270 R4700 R5000 31x31 RM5271-200S qed rm5200
Contextual Info: RM5271 Superscalar Microprocessor with External Cache Interface FEATURES • Dual Issue superscalar microprocessor — 200, 225, 250, 266, 300, 350 MHz operating frequencies — 420 Dhrystone 2.1 MIPS maximum — SPECInt95 7.3, SPECfp95 8.3 maximum • High-performance system interface