PM7390 Search Results

8B10B

Abstract: PM5310 PM5315 PM7390 8b10b decoder
Contextual Info: PMC-Sierra,Inc. PM7390 S/UNI -MACH48 Preliminary Multi-Service Access Device for Channelized Interfaces FEATURES • Single chip ATM and packet processor capable of processing STS-48/STM-16 aggregate payload. • Optionally interprets the incoming AU-3/AU-4 pointers to locate payload

smd marking STPA

Abstract: smd code STPA pn 150bh RS7310 DELTA 18AF D1 SMD CODE MARKING SMD transistor n36 RS7210 18AF smd diode marking A38
Contextual Info: Multi-Service Access Device For Channelized Interfaces Telecom Standard Product Data Sheet Production PM7390 S/UNI-MACH48 MULTI-SERVICE ACCESS DEVICE FOR CHANNELIZED INTERFACES S/UNI- R MACH48 Data Sheet Proprietary and Confidential Production Issue 4: December 2001

UNIMACH-48

Abstract: optical transceiver STM 1 8B10B PM5310 PM5315 PM7390 MACH48 prbs generator
Contextual Info: PMC-Sierra,Inc. PM7390 S/UNI -MACH48 Preliminary Multi-Service Access Device for Channelized Interfaces FEATURES • Single chip ATM and packet processor capable of processing STS-48/STM-16 aggregate payload. • Optionally interprets the incoming AU-3/AU-4 pointers to locate payload

m9845

Abstract: PM5310-BI CHESS PM5316-BI PM5372 PM5372-BI PM7390-BI PMC-1991797 marking PM5316
Contextual Info: CHESS PRELIMINARY CHESS CHIPSET APPLICATION NOTE PMC-1991797 ISSUE 2 PM5372 CHESS USER’S GUIDE CHESS S/UNI- MACH48 PM7390-BI CB924102A M9845 TSE TBS PM5372-BI CB924102A M9845 PM5310-BI CB924102A M9845 ® SPECTRA- ® 155-QUAD PM5315-BI CB924102A M9845

PM7390-BI

Abstract: MACH48 1878H DS35112 STS-48C PM7390 2-1250A 1868H D28Ch
Contextual Info: PM7390 S/UNI MACH48 PRELIMINARY APPLICATION NOTE PMC-2001532 ISSUE 2 CONFIGURING THE PM7390 S/UNI MACH48 PM7390 CONFIGURING THE PM7390 S/UNI MACH 48 PRELIMINARY ISSUE 2: FEBRUARY 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

zener 9A2

Abstract: zener 12a2 zener 12B2 5B2 bridge rectifier ic zener 10B2 10b2 zener diode zener 11a2 12B1 ZENER zener 10B1 5b1 bridge rectifier ic
Contextual Info: PM7390 S/UNI MACH48 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 S/UNI-MACH48 REFERENCE DESIGN PM7390 S/UNI-MACH48 REFERENCE DESIGN ISSUE 2:FEBRUARY 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PM7390 S/UNI MACH48

PM5310

Abstract: PM5315 PM5372 PM7390
Contextual Info: PM7390 S/UNI -MACH48 PMC-Sierra,Inc. Multi-Service Access Device for Channelized Interfaces FEATURES • Single chip ATM and packet processor capable of processing STS-48/STM-16 aggregate payload. • Optionally interprets the incoming AU-3/AU-4 pointers to locate payload

SPECTRA-9953

Abstract: STS-192 STS-48 PM5317
Contextual Info: PM5317 SPECTRA-9953 Advance SONET/SDH Payload Extractor/Aligner for 9953 Mbit/s FEATURES • Monolithic single channel STS192/STM-64 or quad channel STS48/STM-16 SONET/SDH Payload extractor/aligner. • Designed for use in interface applications operating at serial

Gigabit Ethernet PHY

Abstract: PM3386 PM5358 PM5381 PM5382 PM7390
Contextual Info: PM3386 S/UNI -2xGE Dual Gigabit Ethernet Controller PMC-1991223 R4 • Standard OC-48 bandwidth Packet/Cell interface. • Compatible with PMC-Sierra devices supporting POS-PHY Level 3, including: • PM5381 S/UNI®-2488 ATM and POS physical layer device.

TsE 151

Abstract: TN-51 equivalent 7K27
Contextual Info: 1: 41 PM TSE Transmission Switch Element Datasheet Released be r, 20 07 10 :3 PM5372 nd ay ,1 6S ep te m TSE HS IN C on Su TRANSMISSION SWITCH ELEMENT Proprietary and Confidential Released Issue 7: November, 2001 Do wn l oa de d by I HS Pa r ts Ma na g

applications of prbs generator

Abstract: LVDS ip PM5310 PM5315 PM5372 PM5379
Contextual Info: PMC-Sierra,Inc. PM5310 TBS Preliminary TelecomBus Serializer for 2.5 Gbit/s Interconnect FEATURES • Encodes data from the Incoming parallel TelecomBus to a set of four working, a set of four protection, and a set of four auxiliary 777.6 Mbit/s LVDS serial TelecomBus links with extended

Contextual Info: PM5324 ARROW 1x192 SONET/SDH Transport Framer/Aggregator for OC-48 and OC-192 5: 49 AM Released Product Brief • Detects and inserts transport and path BIP-8 errors B1, B2, B3 . :1 Product Overview 01 2 01 il, 2 2A pr Th • • GL OB AL PV • • on •

PM5324

Abstract: PM5374 STM-16 STM-64 STS-48
Contextual Info: PM5324 ARROW-1x192 Advance, Issue 1 SONET/SDH Transport Framer/Aggregator for OC-48 and OC-192 FEATURES • SONET/SDH framer/aggregator for use in channelized STS-192/STM-64 and STS-48/STM-16 applications. • 10 Gbit/s aggregate capacity. The framer can be configured to support:

PM5379

Abstract: 4X4X2 PM5307 PM5317 PM5372 PM5374 PM7390 SPECTRA-9953 UNI-9953 time slot interchange diagram
Contextual Info: PM5307 TBS-9953 Preliminary 9.953 Gbit/s TelecomBus Serializer FEATURES 4 x 2.488 Gbit/s to 3 x 4 x 2.488 Gbit/s W,P,A Supports redundant working/protection time-space-time switch fabrics, including the PM5372 TSE and PM5374 TSE-160 devices. Supports STS-192c/STM-64c, STS48c/STM-16c, STS-12c/STM-4c, and

Contextual Info: 05 PM TelecomBus Serializer Data Sheet Released ,1 6S ep te m be r, 20 07 10 :2 9: PM5310 IN C on Su nd ay TBSTM DATA SHEET Proprietary and Confidential Released Issue 7 : November, 2001 Do wn l oa de d by I HS Pa r ts Ma na g em en tI nc .o fI HS TelecomBus Serializer

3047H

Abstract: 216C2 tl 3282H 14164 1994 T25 4 F8 1N60H AP 1531 216-0216 Am386 x6729
Contextual Info: 39 AM S/UNI 9953 ASSP Telecom Standard Product Data Sheet Released 10 Ma y ,2 00 5 02 :2 6: PM5390 Tu es da y, S/UNI® 9953 Data Sheet Do wn lo a de d by sa tis h d of ag er rt on SATURN® USER NETWORK INTERFACE for 9953 MBIT/S Proprietary and Confidential

PM5332

Abstract: OC-48 OC48 PM5363 PM8611 STS-48 spectra head
Contextual Info: Preliminary PM5332 SPECTRA-1x2488 Channelized STS-48/STM-16 Framer with Integrated Clock/Data Recovery FEATURES • 2.5 Gbps SONET/SDH payload extractor/aligner. Supports Transport Section and Line and Path overhead termination, STS-1 granularity pointer

Contextual Info: 0: 22 PM S/UNI 9953 ASSP Telecom Standard Product Data Sheet Released Mo nd ay ,1 3M ar S/UNI® 9953 ch ,2 00 6 10 :1 PM5390 Data Sheet Proprietary and Confidential Released Issue 9 : February 2006 Do wn l oa de d by C on te nt T ea m of Pa rtm in er In

Contextual Info: 0: 38 AM TBS 9953 ASSP Telecom Standard Product Data Sheet Released sd ay ,0 5F eb ru ar y, 20 03 10 :4 PM5307 In co n W ed ne TBS™ 9953 Data Sheet Released Issue 6: January 2003 Do wn lo ad e d by Co nt en tT ea m of Pa rtm in er OC-192 TelecomBus Serializer

Contextual Info: 3: 18 AM TBS 9953 ASSP Telecom Standard Product Data Sheet Released id ay ,0 7F eb ru ar y, 20 03 06 :2 PM5307 in er In co n Fr TBS™ 9953 Data Sheet Released Issue 6: January 2003 Do wn lo ad e d by Co nt en tT ea m of Pa rtm OC-192 TelecomBus Serializer

GR-253-CORE

Abstract: PM5316 PM5363 PM7390
Contextual Info: PMC-Sierra,Inc. PM5316 SPECTRA-4x155 Preliminary Quad Channel 155 Mbit/s SONET/SDH Framer and Aligner FEATURES • The entire SONET/SDH transport and path overheads are extracted to and inserted from dedicated pins. • Frames to the SONET/SDH receive stream and inserts framing bytes and

2000-327

Abstract: ADM processor regenerator in optical GR-253-CORE PM5316 PM5363 PM7390 PMC cross reference
Contextual Info: PM5316 SPECTRA-4x155 PMC-Sierra,Inc. Quad Channel 155 Mbit/s SONET/SDH Framer and Aligner FEATURES • Monolithic four channel SONET/SDH Payload Extractor/Aligner for use in STS-3 STM-1/AU-3 or STS-3c (STM1/AU-4) interface applications, operating at serial interface speeds of

processor cross reference

Abstract: regenerator in optical PM4388 PM5342 PM5362 PM7364 PM7390 PM8313
Contextual Info: PM5342 SPECTRA -155 PMC-Sierra,Inc. SONET/SDH Payload Extractor/Aligner FEATURES Transmit Ring Control Port Transmit O/H Insert • Available in a 256-pin, Super Ball Grid Array SBGA package. • Supports industrial temperature range (-40°C to 85°C) operation.

data scrambler

Abstract: PM5307 PM5374 STS-192 STS-48 time slot interchange diagram tsec
Contextual Info: PM5374 TSE-160 Preliminary 160 Gbit/s Transport Switching Element • Supports multi-plane inverse multiplexed switch architectures in conjunction with other CHESS components. • Interfaces to STS-192 devices by aggregating 16 STS-12, 8 STS-24, or 4 STS-48 equivalent flows.