PC755 Search Results

microprocessor

Abstract: G172
Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

0828H

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

cga motorola

Abstract: PowerPC755 PC755B 2138F CBGA360 MPC7400 PC745 PC755 PCX755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

2138F

Abstract: CBGA360 MPC7400 PC745 PC755 ATMEL 745 PCX755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

hall sensor u18 032

Abstract: CBGA360 MPC7400 PC745B PC755B CBGA-255 atmel 0820 PowerPC755B
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755B 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745B) 733 MIPS at 400 MHz (PC755B) at 641 MIPS at 350 MHz (PC745B) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

PC755BM8

Abstract: MCP 67 MV PC745 PC755M8 PCX755B
Contextual Info: Features • • • • • • PC755BM8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

sram 1mbyte 3.3v

Abstract: 16x16 bga Multi-Chip Package MEMORY TQFP 100 PACKAGE footprint with or without underfill PC755B PCX755B
Contextual Info: PC755B Microprocessor + 1MByte L2-Cache Multi-Chip Module Fact Sheet Main Features • PC755B RISC microprocessor • 8 Mbit of Synchronous Pipelined Burst SRAM configured as 128Kx72 L2-Cache • Extended temperature modules 2.0V (Core)/3.3V (I/0) for industrial and military applications

ATMEL 322

Abstract: atmel 711 PC755B
Contextual Info: 3& 0LFURSURFHVVRU  0%\WH /&DFKH 0XOWL&KLS 0RGXOH DFW 6KHHW 0DLQ )HDWXUHV • PC755B RISC microprocessor • 8 Mbit of Synchronous Pipelined Burst SRAM configured as 128Kx72 L2-Cache) • Extended temperature modules 2.0V (Core)/3.3V (I/0) for industrial and military applications

microprocessors

Abstract: CBGA PC755
Contextual Info: 3& DQG 3& ELW 5,6& 0LFURSURFHVVRUV DFW 6KHHW The PC745 and PC755 microprocessors are high-performance, low-power, 32-bit implementations of the PowerPC Reduced Instruction Set Computer RISC) architecture, specially enhanced for embedded applications. PC745 and PC755 microprocessors differ only in that the PC755 features an enhanced, dedicated

cop interface

Abstract: PC745 PC755M8 PLL VCO MIL-PRF-38535 X755M
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

PowerPC-603e

Abstract: PowerPC603e PC745B PC755B SPECint95
Contextual Info: PC745B/PC755BFS - Rev.1 – 01/11 PC745B AND PC755B PowerPCTM Microprocessors Fact Sheet PC745B and PC755B PowerPC microprocessors are high-performance, low-power, 32-bit implementations of the PowerPC Reduced Instruction Set Computer RISC architecture, specially enhanced for embedded applications. The

PBGA255

Abstract: 25X25 PowerPC755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

TMS 320 C 6X processor

Abstract: 2164A PC745 PC755M8 2164A dynamic ram cop interface l2-dp
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 300 MHz Maximum L2 Cache Frequency = 150 MHz Maximum 60x Bus Frequency = 66 MHz

cga motorola

Abstract: CBGA360 MPC7400 PC745 PC755 N-19 CI-CGA360 PowerPC755
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

ATMEL 745

Abstract: PCX755 PC755B CBGA360 MPC7400 PC745 PC755 PCX745 PC745 PBGA255 C PBGA255
Contextual Info: Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) Selectable Bus Clock (12 CPU Bus Dividers up to 10x)

cga motorola

Abstract: PCX755B IEC C13 pinout Tag 225 600 replacement PC745B PC755B MPC7400 PowerPC755B PC755 20d100
Contextual Info: Features H H H H H H H H H H H H H H H 18.1SPECint95, estimates 12.3 SPECfp95 @400Mhz PC755B 15.7SPECint95, 9SPECfp95 @350Mhz (PC745B) 733 MIPS @ 400Mhz (PC755B) et 641 MIPS@350Mhz (PC745B) Selectable bus clock (12 CPU bus dividers up to 10x) PD typical 6,4W @ 400Mhz, full operating conditions.

PC745

Abstract: PC755M8 PCX755B
Contextual Info: Features • • • • • • PC755M8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz Maximum L2 Cache Frequency = 175 MHz Maximum 60x Bus Frequency = 66 MHz

TMS 320 C 6X processor

Contextual Info: PC755BM8 RISC Microprocessor Multichip Package Datasheet - Preliminary Specification Features • • • • • • PC755BM8 RISC Miprocessor Dedicated 1-megabyte SSRAM L2 Cache, Configured as 128K x 72 21 mm x 25 mm, 255 Ceramic Ball Grid Array CBGA Maximum Core Frequency = 350 MHz

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

tag 8708

Contextual Info: PC755/745 PowerPC 755/745 RISC Microprocessor Datasheet Features • • • • • • • • • • • • • • • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz PC755 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)

sandisk micro sd

Abstract: digital clock using at89s52 microcontroller stepper motor control with avr application notes sandisk micro sd card pin configuration vhdl code for rs232 receiver STK 435 power amplifier Microcontroller AT89S52 vhdl code for ofdm Microcontroller AT89S52 40 pin fingerprint scanner circuit
Contextual Info: Atmel Corporation Atmel Operations Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1 408 441-0311 FAX 1 (408) 487-2600 Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1 (408) 441-0311 FAX 1 (408) 436-4314 Regional Headquarters Microcontrollers

atmel 938

Abstract: PC7447 PC7455 PC7457 TYPE OF SRAM
Contextual Info: Features • • • • • • • • • • • • • • • • • 3000 Dhrystone 2.1 MIPS at 1.3 GHz Selectable Bus Clock 30 CPU Bus Dividers up to 28x 13 Selectable Core-to-L3 Frequency Divisors Selectable MPx/60x Interface Voltage (1.8V, 2.5V)

sk 8050 rf

Abstract: smd diode 815b C8050 schottky C475 DIODE 2C101 m15 fah 001 8 24VDc R5C592 LTN154X1-L02 W83L950 BGA144F
Contextual Info: SERVICE MANUAL FOR 8050 BY: Grass.Ren Repair Technology Research Department /EDVD Feb.2004 8050 N/B Maintenance Contents 1. Hardware Engineering Specification …………………………………………………………………. 1.1 Introduce ……………………………………………………………………………………………….