PB100484 Search Results

60136-2

Contextual Info: N E C ELECTRONICS INC blE D • b4E752S 00353*15 T55 « N E C E M PB100484 L y lM J j\ f 4 ,0 9 6 X 4 - B it NEC Electronics Inc. 100K E C L R A M 7 Description Pin Configurations The ¿PB100484 is a very high-speed 100K interface ECL RAM organized as 4,096 words by 4 bits with openemitter outputs noninverted . It is available in 28-pin

8a5c

Contextual Info: I íPB100484 4,096 X 4-Bit 100 K ECL ra m NEC Electronics Inc. Description Pin Configurations The PB100484 is a very high-speed 100K interface ECL RAM organized as 4,096 words by 4 bits with openemitter outputs noninverted . It is available in 28-pin cerdip or flatpack packages.

iz9ae

Contextual Info: NEC yuPB10 0 4 8 4 4 ,0 96 X 4-BIT 100K E C L RAM NEC Electronics Inc. Description Pin Configurations The /uF’ DB100484 is a very high-speed 100K interface E C L random access memory. The device is organized as 4 K w ords by 4 bits with open em itter outputs

Contextual Info: j k / X Y * H i W AIPB1 0 0 4 8 4 4 ,0 9 6 X 4 -B it NEC Electronics Inc. 100K E C L R A M Description Pin Configurations Th e /tPB 100484 is a very high-speed 100K interface EC L RAM organized as 4,0 96 w ords by 4 bits w ith openem itter outputs noninverted , it is available in 2 8 -p in

DD354

Abstract: IPB100484AB-5
Contextual Info: N E C ELECTRONICS INC m r M4 ’/ * W NEC Electronics Inc. blE D • b4S7555 0D354G1 DST * N E C E PB100484A 4,096 X 4-BIT 100K ECL RAM Description Pin Configurations The PB100484A is a very high-speed 100K interface ECL RAM. It is organized as 4,096 w ords by 4 bits with

Contextual Info: NEC /PB100484A 4,096 X 4-BIT 100K ECL RAM NEC Electronics Inc. Description Pin Configurations The ¿¿PB100484A is a very high-speed 100K interface ECL RAM. It is organized as 4,096 words by 4 bits with noninverted, open-emitter outputs and low power con­

Contextual Info: SEC PB100484A 4,096 X 4-BIT 100K ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configurations T h e /¿PB100484A is a very high-speed 100K interface E C L RAM. It is organized as 4 ,0 9 6 w ords by 4 bits with 2 8 -Pin Cerdip noninverted, open-em itter o u tp uts and low pow er con­