SJ 38
Abstract: qsc 1110 MicroPak-10 dqfn8 SJ38 mac010a M14D M16D jedec sot-23 6 lead MTC14
Contextual Info: Revised February 2004 Logic and Switch Products Ordering Information Ordering Information TinyLogic is a trademark of Fairchild Semiconductor Corporation. CROSSVOLT, FACT, FACT Quiet Series, FAST, FASTr, and MicroPak are trademarks of Fairchild Semiconductor Corporation.
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MS012540
SJ 38
qsc 1110
MicroPak-10
dqfn8
SJ38
mac010a
M14D
M16D
jedec sot-23 6 lead
MTC14
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FIN1027
Abstract: FIN1028 FIN1028M FIN1028MPX M08A MO-229
Contextual Info: Revised June 2003 FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver General Description Features This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels.
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FIN1028
400Mbs
FIN1028
FIN1027,
FIN1027
FIN1028M
FIN1028MPX
M08A
MO-229
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FIN1027
Abstract: FIN1028 FIN1028K8X FIN1028M FIN1028MPX M08A
Contextual Info: Revised May 2004 FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver General Description Features This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels.
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FIN1028
400Mbs
FIN1028
FIN1027,
FIN1027
FIN1028K8X
FIN1028M
FIN1028MPX
M08A
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IPC-7525
Abstract: jedec package MO-220 MO-229 footprint MO-229 MO-226 MLP06J JEDEC Drawing MO-220 7mm IPC-9701 MLP32A Thin Quad flat package mo-220
Contextual Info: Fairchild Semiconductor Application Note September 2005 Revised September 2005 PCB Land Pattern Design and Surface Mount Guidelines for MLP Packages Introduction MLP Package Construction Overview The current miniaturization trend towards higher performance in
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AN-5067
IPC-7525
jedec package MO-220
MO-229 footprint
MO-229
MO-226
MLP06J
JEDEC Drawing MO-220 7mm
IPC-9701
MLP32A
Thin Quad flat package mo-220
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FIN1027
Abstract: FIN1027A FIN1027AM FIN1027AMX FIN1027K8X FIN1027M FIN1027MPX FIN1027MX FIN1028
Contextual Info: Revised June 2003 FIN1027 • FIN1027A 3.3V LVDS 2-Bit High Speed Differential Driver General Description Features This dual driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350 mV which
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FIN1027
FIN1027A
600Mbs
FIN1027
FIN1027A
FIN1028,
TIA/EIA-644
FIN1027AM
FIN1027AMX
FIN1027K8X
FIN1027M
FIN1027MPX
FIN1027MX
FIN1028
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