MAX9209 Search Results

MAX9220EUM

Contextual Info: 19-2864; Rev 1; 10/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215

UTP cat 6 cable

Contextual Info: 19-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9209GUM MAX9213 marking code 56l MAX9213ETM
Contextual Info: 19-2828; Rev 4; 10/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9209GUM MAX9213 marking aaa MAX9213ETM
Contextual Info: 19-2828; Rev 4; 10/07 KIT ATION EVALU E L B AVAILA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

Contextual Info: 19-2828; Rev 5; 3/12 KIT ATION EVALU E L B A IL AVA Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9213 serialize 21 bits of LVTTL/ LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9209ETM MAX9209EUM MAX9210 MAX9211 MAX9213ETM
Contextual Info: 19-2828; Rev 2; 2/04 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

DS90CR215

Abstract: DS90CR217 MAX9209 MAX9210 MAX9211 MAX9213 MAX9215 marking aaa MAX9213ETM
Contextual Info: 19-2828; Rev 3; 6/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

MAX9213ETM

Contextual Info: 19-2828; Rev 3; 6/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

EPS17

Abstract: MAX9220EUM
Contextual Info: 19-2864; Rev 1; 10/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215

MAX9213ETM

Contextual Info: 19-2828; Rev 3; 6/07 Programmable DC-Balanced 21-Bit Serializers Features The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization.

DS90CR216A

Abstract: DS90CR218A MAX9210 MAX9222 MAX9220EUM
Contextual Info: 19-2864; Rev 1; 8/03 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 feature programmable DC balance, which allows isolation between a serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215

NISSEI siodic

Abstract: hp 40-pin lvds connector H617 F-2W-4ME GT17VB-8DP-DS-SB JU1-JU20 max9244eum MAX9209EUM h517 lvds cable
Contextual Info: 19-4270; Rev 0; 9/08 MAX9209/MAX9244 Evaluation Kit Features The MAX9209/MAX9244 evaluation kit EV kit provides a proven design to evaluate the MAX9209 21-bit programmable DC-balanced serializer and the MAX9244 21-bit deserializer with programmable spread spectrum

MAX9213ETM

Contextual Info: 19-2828; Rev 1; 7/03 Programmable DC-Balanced 21-Bit Serializers Features ♦ Programmable DC-Balanced or Non-DC-Balanced Operation ♦ DC Balance Allows AC-Coupling for Ground-Shift Tolerance ♦ As Low as 8MHz Operation Two frequency ranges and two DC-balance default

Contextual Info: 19-2864; Rev 4; 3/05 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/ MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels.

Contextual Info: 19-3641; Rev 1; 10/07 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

aec-q100

Abstract: AEC-Q100-011 G700K TSMC 1P4M MAX1782ETM tsmc cmos 0.11 um tsmc cmos model AC07X-1Z AB8200T MAX1782
Contextual Info: Automotive Qualification Report MAX7042ATJ+ 308MHz/315MHz/ 418MHz/433.92MHz Low-Power, FSK Superheterodyne Receiver Grade 1 32-Lead TQFN 5 x 5 mm AEC-Q100 Rev. F Tests MSL 1 - Preconditioning PC Biased HAST (HAST) 9 9 9 Lot # 2 (Q43ACQ001B) MAX1499EHJ Maxim

AN3821

Abstract: MAX9209 MAX9214 MAX9222 MAX9238 MAX9242 MAX9244 MAX9246
Contextual Info: Maxim > App Notes > AUTOMOTIVE CLOCK GENERATION AND DISTRIBUTION HIGH-SPEED SIGNAL PROCESSING MISCELLANEOUS CIRCUITS HIGH-SPEED INTERCONNECT Keywords: 21-bit multiple input channel deserializers, skew margin measurement, jitter tolerance, clock jitter, data

Contextual Info: 19-3954; Rev 2; 6/07 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

Contextual Info: 19-3954; Rev 1; 10/06 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance Features The MAX9242/MAX9244/MAX9246/MAX9254 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A separate parallel-rate LVDS clock

HDMI to vga pinout

Abstract: MAX9180 lvds 26 pin MAX9259 MAX9374 MAX9384 Video sync splitter vga SK4401 HDMI to VGA Cable diagram MAX9324
Contextual Info: High-Speed Interconnect 8th Edition February 2009 Industry’s most versatile portfolio of high-speed interface ICs Automotive SerDes for video and audio data Rear-Seat Entertainment Navigation Safety Cameras Fanout buffers, muxes, and crosspoint switches for clock and data distribution

ANSI/TIA/EIA-644

Abstract: MAX9232 MAX9232EUM
Contextual Info: XX-XXXX; Rev 0; 9/05 Programmable Spread-Spectrum and DC-Balance 21-Bit Deserializer Features The MAX9232 deserializes three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A separate parallel-rate LVDS clock provides the timing for deserialization. The MAX9232 features spread-spectrum capability, allowing the output data and clock

max9234

Abstract: MAX9234EUM MAX9236EUM MAX9238
Contextual Info: 19-3641; Rev 0; 4/05 Hot-Swappable, 21-Bit, DC-Balanced LVDS Deserializers The MAX9234/MAX9236/MAX9238 deserialize three LVDS serial-data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel-rate LVDS clock received with the LVDS data streams provides timing for

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

Contextual Info: 19-2864; Rev 5; 11/07 Programmable DC-Balance 21-Bit Deserializers The MAX9210/MAX9214/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing