IDT74LVC162501A Search Results
IDT74LVC162501A Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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LVC162501A
Abstract: SO56-2
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Original |
idt74lvc162501a18-bit250psmil-std-883+5 | |
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Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O D E S C R IP TIO N : FEATURES: - Typical - ESD > 2000V per MIL-STD-883, Method 3015; tsK o (Output Skew) < 250ps > 200V using machine model (C = 200pF, R = 0) - IDT74LVC162501A |
OCR Scan |
18-bitidt74lvc162501a62501a48-pin+1 | |
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Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: - power 18-bit registered bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is |
OCR Scan |
18-bit250psmil-std-883200pf+3 | |
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Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT TOLERANT I/O IDT74LVCH16501A IDT74LVCH162501A IDT74LVC16501A ADVANCE INFORMATION FEATURES: DESCRIPTION: • Common features: These 18-bit registered transceivers are built using ad vanced dual metal CMOS technology. These high-speed, low |
OCR Scan |
18-bitidt74lvch16501aidt74lvch162501aidt74lvc16501a+3 | |
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Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: - power 18-bit registered bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is |
OCR Scan |
18-bit250psmil-std-883200pf+5 |