LVC162501 Search Results

Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: - power 18-bit registered bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

LVC162501A

Abstract: SO56-2
Contextual Info: LVC162501A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER W/ 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: LVC162501A ADVANCE INFORMATION DESCRIPTION:

Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O FEATURES: - power 18-bit registered bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is

Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O D E S C R IP TIO N : FEATURES: - Typical - ESD > 2000V per MIL-STD-883, Method 3015; tsK o (Output Skew) < 250ps > 200V using machine model (C = 200pF, R = 0) - LVC162501A