ICS50 Search Results

moa2

Abstract: 7816-6A1 HC 8332 SL2FCS5001 SL2FCS5101 i-code 2 tag chip SOT500AA1 ICODE SLI DSFI ICODE SLI-L
Contextual Info: SL2 ICS50/SL2 ICS51 I•CODE SLI-L/I•CODE SLI-L HC Rev. 3.0 — 14 March 2007 136430 Product data sheet PUBLIC 1. General description The I•CODE SLI-L/I•CODE SLI-L HC IC is a dedicated chip for smart label applications with the need for a leaner custom-specific command set, smaller memory and/or a

ICS502I

Abstract: ICS502 ICS502M ICS502MI ICS502MIT ICS502MT ICS570B
Contextual Info: ICS502 LOCO PLL Clock Multiplier Description Features The ICS502 LOCO™ is the most cost effective way to generate a high quality, high frequency clock output and a reference from a low frequency crystal or clock input. The name LOCO stands for LOw Cost Oscillator,

501B

Abstract: ICS501B ICS570B
Contextual Info: DATASHEET ICS501B LOCO PLL CLOCK MULTIPLIER Description Features The ICS501B LOCOTM is the most cost effective way to generate a high-quality clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to

4 pin loco crystal oscillator

Abstract: ICS502MILF ICS502I AS 108-120 MDS-502 ICS502 ICS502M ICS502MI ICS502MIT ICS502MLF
Contextual Info: ICS502 LOCO PLL CLOCK MULTIPLIER Description Features The ICS502 LOCOTM is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator,

ICS503

Abstract: ICS503M ICS503MT motherboard electronic circuit diagram
Contextual Info: ICS503 LOCO PLL Clock Multiplier Description Features The ICS503 is a member of the LOCO™ family, the most cost effective way to generate a high quality, high frequency clock output from a low frequency crystal or clock input. The name LOCO stands for LOw Cost

ICS504

Abstract: ICS504M ICS504MT
Contextual Info: PRELIMINARY INFORMATION ICROCLOCK ICS504 Intel i740 Graphics Clock Source Description Features The ICS504 is the most cost effective way to generate a high quality, high frequency clock for Intel’s i740 graphics controller. It also provides a 13.5 MHz clock output for the video encoder.

M7216

Abstract: Crystal 16 MHz 10 pF clock multiplier TTL 60 duty cycle
Contextual Info: ICS501 LOCO PLL CLOCK MULTIPLIER Description Features The ICS501 LOCOTM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed

Contextual Info: PRELIMINARY INFORMATION ICS508 PECL to CMOS Converter Description Features The ICS508 is the most cost effective way to generate a high quality, high frequency CMOS clock output from a PECL clock input. The ICS508 has separate VDD supplies for the PECL input buffer and the output buffer allowing

ICS501I

Contextual Info: BACK ICROCLOCK ICS501 LOCO PLL Clock Multiplier Description Features The ICS501 LOCO™ is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for LOw Cost Oscillator, as it is designed to replace crystal

ICS501

Abstract: ICS501-DWF ICS501M ICS501MI ICS501MIT ICS501MT ICS570B
Contextual Info: ICS501 LOCOTM PLL CLOCK MULTIPLIER Description Features The ICS501 LOCOTM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed

M6412

Abstract: clock multiplier TTL 60 duty cycle 5126w
Contextual Info: DATA SHEET ICS501 ICS501 LOCO PLL CLOCK MULTIPLIER LOCO™ PLL CLOCK MULTIPLIER Description Features The ICS501 LOCOTM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name

Contextual Info: DATASHEET ICS501A LOCO PLL CLOCK MULTIPLIER Description Features The ICS501A LOCOTM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed

ics501i

Abstract: ICS501-DWF ICS501 ICS501-DPK ICS501M ICS501MI ICS501MIT ICS501MT 4 pin loco crystal oscillator
Contextual Info: ICS501 LOCO PLL Clock Multiplier Description Features The ICS501 LOCO™ is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for LOw Cost Oscillator, as it is designed to replace crystal

SECS II wafer map format

Abstract: C075EE UV-tape
Contextual Info: SL2 ICS50 Wafer addendum Rev. 3.0 — 21 March 2007 Product data sheet 136530 PUBLIC 1. General description This specification describes the electrical, physical and dimensional properties of Au-bumped sawn wafers on FFC of I•CODE SLI-L Label ICs on an NXP C075EE process

Contextual Info: DATASHEET PECL CLOCK SYNTHESIZER ICS507-01 Description Features The ICS507-01 is an inexpensive, simple way to generate a low jitter 155.52 MHz or other high speed differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL)

4 pin loco crystal oscillator

Abstract: ICS502I ICS502MI ICS502 ICS502M ICS502MIT ICS502MT
Contextual Info: ICS502 LOCO PLL Clock Multiplier Description Features The ICS502 LOCO™ is the most cost effective way to generate a high quality, high frequency clock output and a reference from a low frequency crystal or clock input. The name LOCO stands for LOw Cost Oscillator, as it is designed to replace

crystal 20Mhz

Abstract: ICS501 ICS501D ICS501DW ICS501M ICS501MI ICS501MIT ICS501MT ics501i
Contextual Info: ICROCLOCK ICS501 LOCO PLL Clock Multiplier Description Features The ICS501 LOCO™ is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for LOw Cost Oscillator, as it is designed to replace crystal

Contextual Info: A A ICS501 LOCO PLL Clock Multiplier icro C lock Description Features The ICS501 LOCO™ is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for LOw Cost Oscillator, as it is designed to replace crystal

Contextual Info: ICS501A LOCO PLL CLOCK MULTIPLIER Description Features The ICS501A LOCOTM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed

ICS507-01

Contextual Info: ICS507-01 Demo Board Instructions ICS507-01 Demo Board The ICS507-01 demo board provides a way to quickly evaluate the performance of the ICS507-01 PECL Clock Synthesizer. Power Connect either 3.3 or 5 volts across the VDD and GND header pins. Frequency Selection

333X

Abstract: ICS501A ICS570B 501AMLF 501AMLFT
Contextual Info: DATASHEET ICS501A LOCO PLL CLOCK MULTIPLIER Description Features The ICS501A LOCOTM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed

ICS507-01

Abstract: ICS507-02 ICS507M-01 ICS507M-01I ICS507M-01T MAN09
Contextual Info: ICS507-01/02 PECL Clock Synthesizer Description Features The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz or other high speed differential PECL clock output from a low frequency crystal input. Using Phase-LockedLoop (PLL) techniques, the devices use a standard

501mlf

Abstract: 501MLFT 501milf 501MT ICS501 ICS570B
Contextual Info: DATASHEET LOCO PLL CLOCK MULTIPLIER ICS501 Description Features The ICS501 LOCOTM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace

Contextual Info: ICS507-01/02 PECL Clock Synthesizer Description Features The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz or other high speed differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard