GS9090 Search Results

UCBBJE20-1

Abstract: GS9090A JTAG header 5x2 MAN 1002 37R4 B3S-1002 GS1574A GS9074A IRU1206-33CY SQT-105-01-F-D-RA
Contextual Info: GS9090A A Guide to Designing with the GenLINX III Serial-to-Parallel Converter EB9090 rev 1 Reference Design 35233 - 0 July 2005 1 of 18 GS9090A Reference Design Contents 1. Overview .3

GS9090A

Abstract: RP165 RP168 352M GS9090
Contextual Info: GS9090A GenLINX III 270Mb/s Deserializer for SDI GS9090A Preliminary Data Sheet Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding • Integrated line-based FIFO for data

Contextual Info: GS9090 GenLINX III 270Mb/s Deserializer for SDI and DVB-ASI GS9090 Preliminary Data Sheet Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding • Integrated line-based FIFO for data

Contextual Info: GS9090A GenLINX III 270Mb/s Deserializer for SDI and DVB-ASI GS9090A Preliminary Data Sheet Key Features Description • SMPTE 259M-C compatible descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding • Integrated line-based FIFO for data

Contextual Info: GS9090A GenLINX III GS9090A Preliminary Data Sheet Key Features Description • SMPTE 259M-C compatible descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding • Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI

1uF CAPACITOR

Abstract: GS9090A GS9090B dvb circuit GS9090 Migration from the GS9090 to the GS9090A, GS9090B
Contextual Info: Migration from the GS9090 to the GS9090A, GS9090B GS9090/9090A/GS9090B Information Note The purpose of this document is to explain the differences between the GS9090, GS9090A, and GS9090B in order to enable a smooth migration from the now discontinued GS9090 to either the GS9090A, or GS9090B.

352M

Abstract: GS9090 GS9090A GS9090B RP165 RP168
Contextual Info: GS9090A GenLINX III 270Mb/s Deserializer for SDI and DVB-ASI Key Features Description • SMPTE 259M-C compatible descrambling and NRZI to NRZ decoding with bypass • DVB-ASI 8b/10b decoding • Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet

GS9091B

Abstract: GS9091A combination lock circuit GS9090B cmos switch dvb circuit false GS9090 GS9090A STG719
Contextual Info: GS9090B/GS9091B Applications Circuit for False Lock Recovery GS9090B/GS9091B Information Note This Information Note provides details to the DVB-ASI mode of operation for the GS9090B/GS9091B and is important for migration from the GS9090, GS9090A and the GS9091A. The SMPTE SDI mode does not require the application circuit

RP168

Abstract: STG719 MARK 305M 352M A114B GS9090 GS9090B JESD22 SMPTE352 GS9091
Contextual Info: GS9090B GenLINX III 270Mb/s Deserializer for SDI Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI 8b/10b decoding The GS9090B is a 270Mb/s reclocking deserializer with an internal FIFO. It provides a complete receive solution for

352M

Abstract: GS9090 RP165 RP168 GS9090C
Contextual Info: GS9090 GenLINX III 270Mb/s Deserializer for SDI and DVB-ASI GS9090 Data Sheet Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding • Integrated line-based FIFO for data

Contextual Info: GS9090A GenLINX III 270Mb/s Deserializer for SDI and DVB-ASI Key Features Description • SMPTE 259M-C compatible descrambling and NRZI to NRZ decoding with bypass • DVB-ASI 8b/10b decoding • Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet

Contextual Info: GS9090 GenLINX III 270Mb/s Deserializer for SDI and DVB-ASI GS9090 Data Sheet Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding • Integrated line-based FIFO for data

tiny13v

Abstract: atmel tiny13v SQT-105-01-F-D-RA UCBBJE20-1 Trompeter TINY13V Datasheets EB9090B B3S-1002 37R4 GS9074A
Contextual Info: GS9090B A Guide to Designing with the GenLINX III Serial-to-Parallel Converter EB9090B rev A Reference Design 45339 - 0 August 2007 1 of 19 GS9090B Reference Design Contents 1. Overview .3

SMPTE 310M

Abstract: GS9090A equalizer register fifo atsc 27mhz transmitter circuit GS9074A GS9092A 270MB SMPTE-310M FS1112
Contextual Info: DVB-ASI Using the GS9090A and GS9092A DVB-ASI Application Note Introduction to DVB-ASI DVB-ASI is a method of transmitting compressed digital video MPEG-2 at an uncompressed serial transmission rate. This allows existing SDI infrastructure operating at 270Mb/s to pass video of varying bit-rates. For example, a 19Mb/s

305M

Abstract: 352M A114B GS9090 GS9090B JESD22 RP168 RP+165+smpte
Contextual Info: GS9090B GenLINX III 270Mb/s Deserializer for SDI GS9090B Data Sheet Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding The GS9090B is a 270Mb/s reclocking deserializer with

GS9090ACNE3

Abstract: RP168 352M GS9090 GS9090A GS9090B RP165
Contextual Info: GS9090A GenLINX III 270Mb/s Deserializer Key Features Description • SMPTE 259M-C compatible descrambling and NRZI to NRZ decoding with bypass • DVB-ASI 8b/10b decoding • Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet

352M

Abstract: GS9090A GS9092A
Contextual Info: GS9092A GenLINX III 270Mb/s Serializer for SDI and DVB-ASI GS9092A Data Sheet Key Features Description • SMPTE 259M-C compliant scrambling and NRZI to NRZ encoding with bypass • DVB-ASI sync word insertion and 8b/10b encoding • Integrated Cable Driver

gennum GS9091 device

Abstract: GS9091B GS9091 cs2 105-01 305M 352M GS9090B RP168 STG719
Contextual Info: GS9091B GENLINX III 270Mb/s Deserializer for SDI and DVB-ASI with Integrated Cable Equalizer GS9091B Data Sheet Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding

CSA8000

Abstract: GS9092A
Contextual Info: GS9092A GenLINX III 270Mb/s Serializer for SDI and DVB-ASI Key Features Description • SMPTE 259M-C compliant scrambling and NRZI to NRZ encoding with bypass • DVB-ASI sync word insertion and 8b/10b encoding • Integrated Cable Driver The GS9092A is a 270Mb/s serializer with an internal FIFO

EBK-GS3490-00

Contextual Info: video Featuring New UHD-SDI Solutions Broadcast Video Selector Guide • Equalizers • Cable Drivers • Reclockers • Configurable SDI I/O • SDI Transmitters • SDI Receivers • Crosspoint Switches • Timing Gen-Clocks Spring 2014 End-To-End Portfolio of Broadcast Video Solutions

GV8500

Abstract: gV8501 GS2971A GS2961A GO2929 GS2970A GS2988 QFN 64 8x8 footprint GN1406 GX3146
Contextual Info: Broadcast Video Fall 2010 Product Guide Contents Intro 1 What’s New 2 Crosspoint Switches 3 Equalizers 5 Reclockers 6 Optical Modules 7 Gennum Product Guide 9 Cable Drivers 11 Choosing the Right SerDes 12 Transmitters 13 Receivers 14 Timing GEN-Clocks 15

Gennum GS2971

Abstract: gs2971 cea-861 GO1555 GS1559 GS2970 GS2961 gennum 424M 425M
Contextual Info: Gennum Receivers 3Gb/s SDI Gennum’s new GS2971 and GS2961 are fully integrated and compliant with SMPTE 424M and 425M including support for both Level A and Level B. In addition, these chips are the only solutions providing conversion from Level B to Level A. The full set of included features makes these devices the ideal choice for

Contextual Info: GS9091B GenLINX II 270Mb/s Deserializer for SDI and DVB-ASI Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI 8b/10b decoding The GS9091B is a 270Mb/s equalizing and reclocking deserializer with an internal FIFO. It provides a complete receive solution for SD-SDI and DVB-ASI applications.

Contextual Info: GS4901/00 SD Clock and Timing Generator with GENLOCK GS4901/00 Product Brief Key Features Description Video Clock Synthesis • • • • • Pre-programmed for 4 video clock periods 14.32MHz, 27MHz, 36MHz, and 54MHz Accuracy of free-running clock frequency limited only by