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Contextual Info: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [

D3450

Contextual Info: 74ACT11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS129 - D3450, MARCH 1990 - REVISED APRIL 1993 • * Inputs Are TTL-Voltage Compatible DB, DW OR NT PACKAGE TOP VIEW I * Contains Eight D-Type Flip-Flops I I * Clock Enable Latched to Avoid False Clocking

d204d

Contextual Info: 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS101 - D3420, FEBRUARY 1990 - REVISED APRIL 1993 i * Contains Eight D-Type Flip-Flops * Clock Enable Latched to Avoid False Clocking DW OR NT PACKAGE TOP VIEW * Applications Include: Buffer/Storage Registers, Shift Registers, Pattern

Multimeter fluke 114

Abstract: N10140 4000 Counts Digital Multimeter
Contextual Info: Fluke 114 Electrical Multimeter Technical Data Compact true-rms meter for electrical troubleshooting The Fluke 114 is the troubleshooting tool for “go/no-go” testing. It includes a feature to prevent false readings caused by ghost voltage. Features include:

MC9S08QB8

Abstract: 0M80N
Contextual Info: Freescale Semiconductor Mask Set Errata MSE9S08QB8_0M80N Rev. 1, 5/2010 Mask Set Errata for Mask 0M80N Introduction This report applies to mask 0M80N for these products: • MC9S08QB8 • MC9S08QB4 SE184-FLVD-STOP3: False low voltage detect when exiting stop3

uses of magnitude comparator

Abstract: 9327 AN9327 HC-5509A1 RCMA
Contextual Info: TM No. AN9327 Intersil Telecom October 1993 HC-5509A1 RING TRIP COMPONENT SELECTION Author: Ken Feldhaus Introduction Any linecard ringing implementation requires the removal of the ring signal from the subscriber line within a specified time after the subscriber goes off-hook. This prevents the ring signal from causing discomfort to the subscriber. It is also important that the system not falsely ring trip detect off-hook while

Contextual Info: 74AC11378 HEX D–TYPE FLIP–FLOP WITH CLOCK ENABLE SCAS150 – APRIL 1991 – REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE Contains Six D-Type Flip-Flops Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage

TIP31 NPN Transistor

Abstract: FAN MOTOR CONTROL SPEED WITH LM339 fan speed control lm339 theory of lm358 opamp ic FAN SPEED control WITH LM339 MISSING PULSE DETECTOR CIRCUIT FAN MOTOR CONTROL SPEED WITH LM358 1n4001 silicon diode PWM 12V fan speed control circuit FAN MOTOR CONTROL SPEED WITH LM358 PWM
Contextual Info: Application Note 34 Micrel Application Note 34 Fan Health Monitoring and the MIC502 by Micrel Applications Staff These pulses must be blanked in order to avoid a false indication of fan operation. Although some fans exhibit very clean current waveforms at commutation, others tend to ring

EXEL MICROELECTRONICS

Abstract: XLS48C64-200 XLS48C64-250 XLS48C64C-150
Contextual Info: XL48C64 M IC R O E L E C T R O N IC S . IN C FEATURES • ■ ■ ■ ■ ■ ■ ■ 8192 x 8 Bit E2PRO M Single 5-Volt Supply Fast Data Access: 150ns Low Power Requirements: - 100/u.a Standby - 100/u.a Quiescent Automatic Write Cycle Time-out Foolproof False Write

PLA relay

Abstract: D2425D D2440D H12D4825D H12D4840D
Contextual Info: Dual Relays 25-40Amp • 120/240, 480 Vac« AC Output • Two totally independent AC output relays come in a single standard panel­ mount package. Utilizing an AC switch output w ith internal snubber, relays provide greater protection against false triggering. Model choices include zerovoltage or random turn-on phase con­

X391

Contextual Info: ThomasiBetts Terminators GLOSSARY A c tiv e N egation: A technique which quickly drives a signal back to a false state, facilitating faster transmission of data. A c tiv e T e rm in a tio n : A terminator which has the ability to provide accurate voltage reference and/or impedance

Contextual Info: 74AC11378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS150 − APRIL 1991 − REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE Contains Six D-Type Flip-Flops Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage

SE140

Abstract: 2M12J se139 MCF51QE128 MCF51QE32 MCF51QE64 MCF51QE96
Contextual Info: Freescale Semiconductor Mask Set Errata MSEF51QE128_2M12J Rev. 2, 5/2010 Mask Set Errata for Mask 2M12J Introduction This report applies to mask 2M12J for these products: • MCF51QE128 • MCF51QE96 • MCF51QE64 • MCF51QE32 SE184-FLVD-STOP3: False low voltage detect when exiting stop3

LED Drive smps circuit diagram

Abstract: TEA1101 NTC resistor T24 120 VAC to DC smps circuit diagram 7 pin dil smps power control ic APPLICATION NOTES OF SMPS CHARGERS 15A POWER TRANSISTOR FOR SMPS 7 pin SMPS LED monitor circuit diagram SMPS CIRCUIT DIAGRAM
Contextual Info: Preliminary specification Philips Semiconductors Integrated Circuits Battery monitor for NiCd and NiMH chargers FEATU RES • Accurate detection of fully charged batteries by currentless - d V sensing • Digital filtering of the battery voltage to avoid false - d V

e10s

Abstract: AN3892 MPR121
Contextual Info: Freescale Semiconductor Application Note AN3892 Rev 0, 9/2009 MPR121 Jitter and False Touch Detection INTRODUCTION Touch acquisition takes a few different parts of the system in order to detect touch. The baseline filter and touch detection are tightly coupled. The purpose of the touch detection block is to use the baseline value and the 2nd level filter data to determine

TC670

Abstract: C04-120 TC670ECH TC670ECHTR C0412
Contextual Info: M TC670 Tiny Predictive Fan Failure Detector Features General Description • Fan Wear-Out Detection for 2-Wire Linear-Controlled Fans • Replacement System for 3-Wire Fans • Fan Alert Signal when Fan Speed is below Programmed Threshold • CLEAR Capability for Eliminating False Alarm

3000

Abstract: MS3102
Contextual Info: Specifications Hercules Encoders Series 1000/3000 Hall Effect Incremental Rotary Shaft Encoders • Enclosure: Series 1000-2.25" Cube Series 3000-3''x3''x1.5'' NEMA 12/13 or NEMA 4 type Sealing Flush or Flanged Base • Inherent Anti-Jitter Circuitry prevents false outputs

SN74F377A

Contextual Info: SN74F377A OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993 • • • • • DW OR N PACKAGE TOP VIEW Contains Eight D-Type Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking

sc4150100

Contextual Info: SC4150 Negative Voltage Hot Swap Controller POWER MANAGEMENT Description Features The SC4150 is a negative voltage hotswap controller that allows the insertion of line cards into a live backplane. ‹ Programmable slew of the inrush current when The inrush current is programmable and closed loop operation limits the maximum current even under short circuit conditions. A built in timing circuit prevents false shutdown. The signal from the drain voltage is fed to the

74ACT11377

Abstract: D3450
Contextual Info: 74ACT11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS129 – D3450, MARCH 1990 – REVISED APRIL 1993 • • • • • • • • • DB, DW OR NT PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Contains Eight D-Type Flip-Flops Clock Enable Latched to Avoid False

Contextual Info: YD2410 YOUDA INTEGRATED CIRCUIT TONE RINGER—YD2410 DESCRIPTION The YD2411 is a bipolar integrated circuit designed for telephone bell replacement. FEATURES *Low Power Dissipation *Adjustable output tune *Adjustable Switching Rate *Built-in Hysteresis Prevents False Triggering

video sync detector

Abstract: MAX7461 MAX7461EUK LPF SOT23-5
Contextual Info: 19-0553; Rev 0; 5/06 Loss-of-Sync Alarm The MAX7461 single-channel loss-of-sync alarm LOS provides composite video sync detection in NTSC, PAL, and SECAM standard-definition television (SDTV) systems. The MAX7461’s advanced detection circuitry delivers robust performance by preventing false lossof-sync alarms due to noise. The device accepts an

T04 transistor

Abstract: transistor t04 transistor t06 t06 TRANSISTOR AT80C51RA2 atmel 8051 datasheet TS80C51RB2 TS87C51RB2 36425 Atmel AT80
Contextual Info: Active Errata List • • • • • • UART/Reception in Modes 1, 2 and 3/UART False Start Bits Detection During UART Reception, Clearing REN May Generate Unexpected IT JBC/Double IT When External IT Occurs During JBC Instruction Timer2/Downcounter Mode/Double IT With Slow External Clock

Contextual Info: 74AC11379 QUAD D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS104 − MARCH 1990 − REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE TOP VIEW Contains Four Flip-Flops with Double-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage