EP2S15 Search Results

EP2S15

Abstract: DM5R DQ16L3 DM20R diode AA16 dm18r Pin Out For EP2S15
Contextual Info: Pin Information for the Stratix II EP2S15 Device Version 2.1 Note 1 IO IO IO IO IO IO IO IO VREFB2N0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB2N1 IO IO IO IO IO IO IO PT-EP2S15-2.1 Copyright 2007 Altera Corp. DIFFIO_RX18p

PCI-M32

Abstract: verilog code for MII phy interface
Contextual Info: Network Interface Features − Support for 10/100 Mbps data transfer rate MAC-PCI Ethernet MAC Controller with PCI Host Interface Megafunction − Media Independent Interface MII for 10/100 Mbps operation − Automated MII Management interface Data Link Layer Functionality

rc5 protocol

Abstract: EP2C5T144C6 RC5 encoder RC5 philips RC5 IR philips RC5 decoder philips RC5 protocol altera manchester RC5 decoder EP1C3T100C6
Contextual Info:  5-bit address and 6-bit com- mand length IR-RC5-E and -D Infrared Encoder and Decoder Megafunctions  Bi-phase coding also known as Manchester coding  Carrier frequency of 36 kHz as per the RC5 standard  Fully synchronous design Encoder Features

intel 8051 Arithmetic and Logic Unit -ALU

Abstract: Memory Management 8051 8051 address decoder verilog code for ALU implementation 80C31 80C51 ASM51 SAB80C537 verilog code for 32 BIT ALU implementation verilog code for 8051
Contextual Info:  Control Unit − Eight-bit instruction decoder for MCS 51 instruction set R8051XC-EP 8051-Compatible Microcontroller Megafunction An economical, entry-point, fixed-configuration megafunction that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of eight times faster.

HSCX 82525

Abstract: R8051XC-HDLC hdlc R8051XC
Contextual Info:  LAPB/LAPD controlling machine providing  modulo 8 frame numbering HDLC  modulo 128 frame numbering HDLC Protocol Controller Megafunction  automatically generated res-  one- or two-byte addressing ponses  Serial Peripheral Interfaces  Bit stuffing

rgb TO HDMI convert chip

Abstract: AD9889B CH7301C lcd qvga 320x240 Sitronix ST7787 ADV7120 RGB24 EP3C40-6 YCbCr TO TFT converter graphic lcd module 320x240
Contextual Info: Generates color and control data for standard displays in the following resolutions: DISPLAY-CTRL High-Resolution Display Controller Megafunction Implements a controller that accepts video data and works with a digital/analog converter DAC to drive standard QVGA (320x240) to WUXGA (1920x1200) displays.

Contextual Info:  Interfaces directly to Mobile and SDR-SDRAMCTRL Single Data Rate Mobile SDRAM Controller Megafunction ordinary Single Data Rate SDR SDRAM chips and registered/unbuffered DIMMS  Supports address space up to 2G (230 words) and – one to eight chip selects,

MAC-1G

Abstract: EP2S15-3 TLSM
Contextual Info: Network interface features o Supports data transfer rates of 10/100/1000 Mbps MAC-1G 1-Gigabit Ethernet Media Access Controller Megafunction o MII/GMII Media Independent Interface o Optional RMII, SMII o PHY management interface* Data link layer functionality

dct verilog code

Abstract: EP20K100E-1 EP1S10-C5
Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies IDCT  Low gate count 2-D Inverse Discrete Cosine Transform Megafucntion  Low latency (86 cycles)  Single clock cycle per sample operation Design Quality

dct verilog code

Abstract: EP20K100E-1 2d dct block
Contextual Info: Ease of Integration & Performance  High clock speed >250 MHz in 0.18um ASIC technologies DCT  Low gate count 2-D Forward Discrete Cosine Transform Megafunction  Low latency (87 cycles)  Single clock cycle per sample operation Design Quality  Fully compliant with the JPEG

SpeedTags

Contextual Info: Scalado CAPSTM Compliance  Integrates SpeedTagsTM tech- nology SVE-JPEG-E JPEG Features SpeedView Enabled JPEG Encoder Megafunction  Programmable quantization  Programmable Huffman Tables two DC, two AC and tables (four)  Up to four color components

EPCS16

Abstract: epcs128 1064V
Contextual Info: 1. Altera Configuration Devices CF52001-2.4 Introduction During device operation, Altera FPGAs store configuration data in SRAM cells. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. You can configure Stratix® series, Cyclone®

320x240 VHDL

Abstract: sharp 640x240 lcd LCD controller 240x320 DVI VHDL DB9000 fpga TFT altera DB9000AVLN Cyclone TFT DVI verilog DB9000 tft
Contextual Info: Digital Blocks DB9000AVLN Semiconductor IP Avalon Bus TFT LCD Controller General Description The Digital Blocks DB9000AVLN TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the Avalon Bus to a TFT LCD panel. In an Altera FPGA, typically, the microprocessor is a NIOS II processor and frame buffer

automatic change over switch circuit diagram

Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90
Contextual Info: Section II. Clock Management This section provides information on clock management in Stratix II GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.

cd 1619 CP

Abstract: RX SOP 1738 bc 494 b f.m transmitter Schematics AL 1450 DV hp 2212 sdc 2025 AL 2450 dv circuit diagram toggle switches 2041 BY TRANSISTOR BC 187 vhdl code for 16 prbs generator
Contextual Info: Stratix II GX Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIIGX5V1-4.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

CQ 419

Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90
Contextual Info: Section III. Memory This section provides information on the TriMatrix embedded memory blocks internal to Stratix II GX devices and the supported external memory interfaces. This section contains the following chapters: Revision History Altera Corporation

pin configuration 1K variable resistor

Abstract: EPC1441 EPC16 EPCS128 EPCS16 EPCS64 EPC8QC100 EPC8QC100 Pinout fpga JTAG Programmer Schematics ic 11105 circuits diagraM
Contextual Info: Configuration Handbook Preliminary Information 101 Innovation Drive San Jose, CA 95134 www.altera.com Config-1.3 September 2007 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

FBGA 152

Abstract: 68 ball fbga thermal resistance FBGA1020 78 ball fbga thermal resistance EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 FBGA-484
Contextual Info: 10. Package Information for Stratix II & Stratix II GX Devices SII52010-4.3 Introduction This chapter provides package information for Altera Stratix® II and Stratix II GX devices, including: • ■ ■ Device and package cross reference Thermal resistance values

altera stratix II fpga

Abstract: DDR2 sdram pcb layout guidelines vhdl code for watchdog timer of ATM
Contextual Info: Stratix II Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SII5V2-4.3 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

EP4CE15

Abstract: EP4CE22 EP2AGX190 interlaken EP4CGX150 EP4CGX30 EP3SE50 EP4CE30 HC210 EP1C12
Contextual Info: Quartus II Software Version 10.0 SP1 Device Support RN-01057 Release Notes This document provides late-breaking information about device support in the 10.0 SP1 version of the Altera Quartus® II software. For information about disk space and system requirements, refer to the readme.txt file in your

CQ 419

Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90
Contextual Info: Section II. Memory This section provides information on the TriMatrix embedded memory blocks internal to Stratix II devices and the supported external memory interfaces. This section contains the following chapters: Revision History Altera Corporation

EPCS16SI8N

Abstract: EPCS128 EPCS64SI16N EPCS16 EPCS 16 soic EPCS4 EPCS64 h5800 pin information ep3c5 EPCS1SI8N CG-250
Contextual Info: 14. Serial Configuration Devices EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128 Data Sheet C51014-3.1 Introduction The serial configuration devices provide the following features: • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 1 Altera Corporation May 2008

AGX52011-1

Abstract: EPC16 EPCS128 EPCS16 EPCS64 vhdl code uart altera
Contextual Info: Section VI. Configuration& Remote System Upgrades This section provides configuration information for all of the supported configuration schemes for Arria GX devices. These configuration schemes use either a microprocessor, configuration device, or download

B17C

Abstract: teradyne flex tester AGX52001-1 AGX52002-1 AGX52003-1 AGX52004-1 AGX52005-1 AGX52006-1 AGX52007-1 AGX52008-1
Contextual Info: Arria GX Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com AGX5V2-1.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and