DS90UR124 Search Results

DS90UR241

Contextual Info: 24 Timing and Control Clock Recovery TPWDNB • RCLK — PASS SERIALIZER - DS90UR241 DESERIALIZER - DS90UR124

DS99R421

Contextual Info: STP DS90UR124 DOUT- RIN+ RIN- Up to 10 meters rt = ioon DOUT+ Rx - DESERIALIZER

Contextual Info: DS90UR124, DS90UR241 www.ti.com SNLS231M – SEPTEMBER 2006 – REVISED OCTOBER 2011 DS90UR241Q DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Check for Samples: DS90UR124, DS90UR241 FEATURES 1 • • • 23 • •

G7 mic

Abstract: I2S bridge I2S to SPI bridge audio automatic gain control Bluetooth IC bluetooth 1.2 spi interface ic audio adc dac national automatic gain control ic audio bluetooth controller DS90UR124
Contextual Info: Automotive Infotainment Solutions Rear Seat Entertainment: Audio Over LVDS TCLK RIN+ RIN- DIN22 DIN22 DOUT+ DOUT- FPD – Link II DS90UR241 DAC LM49370 DS90UR124 • Rear seat entertainment • I²S DAC subsystems • Stereo HP output • I2S/PMC bridge for easy Bluetooth communication

"Signal Conditioning"

Abstract: DS25CP102Q
Contextual Info: DS25CP102Q 2x2 CROSSPOINT DS90UR241Q i r EQ PE SIGNAL CONDITIONING L^> 1 TO 24 I I MONITOR 1 GREEN BLUE \ V DS90UR124Q L_ ^> K 1 TO 24 I I MONITOR 2 GREEN BLUE \ V DS90UR124Q s_/

RGB666

Abstract: LVDS connector 40 pins DS90C124 DS90UR124 giga media converter LVDS 30 pin connector cable LVDS connector 40 pins NAME SDI SERIALIZER SWITCHING NOISE SUPPRESSION OF LVDS SERIALIZER AEC-Q100
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

DS90C124

Abstract: AEC-Q100 AN-1217 DS90C241 DS90UR124 DS90UR241 ISO10605
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

Contextual Info: DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Check for Samples: DS90UR124Q, DS90UR241Q FEATURES APPLICATIONS • • •

Contextual Info: DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Check for Samples: DS90UR124Q, DS90UR241Q FEATURES APPLICATIONS • • •

DS90UR124

Abstract: AEC-Q100 AN-1217 DS90C124 DS90C241 DS90UR241 ISO10605 ISO-10605 air discharge verification
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

DS90UR124

Abstract: AN-1217 DS90C124 DS90UR241 ISO10605 245RL
Contextual Info: September 2006 DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by

DS90C124

Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

DS90C124

Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

DS90C124

Contextual Info: DS90UR124,DS90UR241 DS90UR241Q DS90UR124Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Literature Number: SNLS231M October 5, 2011 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset General Description

aec-q100

Abstract: DS25CP152 DS10CP152Q LLP-40 DS10CP152 DS10CP154 DS25CP102 DS25CP104 SOIC-16 navigation computer
Contextual Info: Automotive Infotainment Applications Drive 10m Cables to Multiple Displays with SerDes and PowerWise Crosspoint Switches DS90UR241Q DS90UR124Q 2X2 Crosspoint Navigation Computer 24 to 1 1 to 24 Entertainment System 24 to 1 1 to 24 Monitor1 1 Display Monitor2 2

DS90UR241Q

Contextual Info: DS90UR241Q I I g re e n "^^ BLUE^> DS90UR124Q □üO 1 TO 24 | G R EE N ^^ I BLUE^ > DS90UR124Q MONITOR 1

DS90C124

Abstract: AEC-Q100 AN-1217 DS90UR124 DS90UR241 ISO10605
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

second order low pass filter

Abstract: RGB666 DS90C124
Contextual Info: DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description • User selectable clock edge for parallel data on both The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with

ROUT21

Abstract: ROUT13 DS90UR124
Contextual Info: DS90UR124 DES VDD VDD cTl Tc5 ± ± t - l cTl VDD VDD R1 RINC10 GPO if used, or tie High (ON) I >- RPWDNB BISTEN GPOs if used, or tie Low (OFF) BISTM ~E Notes: RPWDNB = System GPO REN = High (ON) RRFB = High (Rising edge) RAOFF = Low (Default) PTOSEL = Low (Defaut)

DS90UR124

Abstract: wVGA LCD Tcon 18BIT TCON RGB RGB666 1x10e9 LVDS display tcon wvga DS90C124 DS90UR241 Notebook lcd rgb schematic
Contextual Info: FPD-Link II Display Solutions for Automotive Applications DS90UR241/DS90UR124 1 Panelists • Alex Tan – High Speed Data Path Marketing • John Goldie – High Speed Data Path Applications 2 Objectives • List which automotive applications are targeted for

Contextual Info: DS90UR124Q, DS90UR241Q www.ti.com SNLS231N – SEPTEMBER 2006 – REVISED MARCH 2013 DS90UR124Q DS90UR241Q 5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset Check for Samples: DS90UR124Q, DS90UR241Q FEATURES APPLICATIONS • • •

clc014aje

Abstract: LMV8244 Video sync splitter lm DS34C86 LMH0074SQ DS8921 HV servo thermopile array 2N3960 DP838640 DS8921 equivalent
Contextual Info: Analog Design Guide for Xilinx FPGAs www.national.com/xilinx 2008 Vol. 1 Analog Solutions for FPGAs .2 Design Tools .3 PowerWise Solutions . 4-5 Data Conversion . 6-12 Amplifiers. 13-23

DS90C124

Contextual Info: DS90C241 Serializer and DS90C124 Deserializer Evaluation Kit User’s Manual NSID: SERDES24-35USB Rev 1.5 National Semiconductor Corporation Date: 2/27/2008 Page 1 of 39 Table of Contents TABLE OF CONTENTS . 2

Contextual Info: D S 10C P 152Q DS10CP152Q Automotive 1.5 Gbps 2X2 LVDS Crosspoint Switch Texa s In s t r u m e n t s Literature Number: SNLS295D a l DS10CP152Q Sem iconductor Automotive 1.5 Gbps 2X2 LVDS Crosspoint Switch General Description Features The DS10CP152Q is a 1.5 Gbps 2x2 LVDS crosspoint switch