EPM7256 PIN
Contextual Info: ALTERA bflE CORP D • DS1S372 GGD3272 T7S « A L T EPM7256 EPLD Features □ □ □ □ □ □ High-density, erasable CMOS EPLD based on second-generation MAX architecture 5,000 usable gates Combinatorial speeds with tPD = 20 ns Higher speed versions under development
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ds1s372ggd3272epm7256192-pin+2208-pinepm7256 pin
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EPM7256
Abstract: fp 221 25.b EPM7256-25 EPM7256 PIN EPM7256-20 DDD3271 B1395 HA1084 NN37 KE236
Contextual Info: ALTERA bflE D CORP • DS1S372 GGD3272 T7S « A L T EPM7256 EPLD Features □ □ □ □ □ □ High-density, erasable CMOS EPLD based on second-generation MAX architecture 5,000 usable gates Combinatorial speeds with tPD = 20 ns Higher speed versions under development
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ds1s372192-pin208-pinepm7256+9fp 221 25.bepm7256-25epm7256 pinepm7256-20ddd3271b1395ha1084nn37ke236
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Altera EP1810
Contextual Info: ALTERA CORP 47E D • 05*15372 DQ0211b 376 ■ ALT T ^ to -o / EP1810 EPLD s A N b [m □ □ □ □ □ □ □ □ □ □ High-density replacement for TTL and 74HC High-performance 48-macrocell EPLD with tPD = 20 ns and counter frequencies up to 50 MHz
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000211bep181048-macrocellep1830-20+4ep1830-25ep1830-30ep1830altera ep1810
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Altera EPM5128
Abstract: WKX 62 EPM5016 epm5130 pinouts for 7400 series EPM5064 EPM5192 program EPM5032 EPM5128 PACKAGING PLDS-MAX
Contextual Info: EPM5016 to EPM5192 EPLDs High-Speed, High-Density MAX 5000 Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ Complete family of CMOS EPLDs solves design tasks ranging from fast 20-pin address decoders to 100-pin LSI custom peripherals.
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epm5016epm519220-pin100-pin+915-nsaltera epm5128wkx 62epm5130pinouts for 7400 seriesepm5064program epm5032epm5128 packagingplds-max
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55B0
Abstract: Signal Path designer
Contextual Info: FLEX 6000 Programmable Logic Device Family June 1997, ver. 2 Data Sheet Introduction W ith a prim ary focus on low cost, the Altera FLEX® 6000 device family provides an ideal program m able alternative to high-volume gate-array applications. Because FLEX 6000 devices are programmable, fast design
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epf6010qc208g557c55b0signal path designer |
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r12n10
Abstract: EMP7032 max7000
Contextual Info: Includes MAX7000E M A Y IVI M A 7 0 0 0 / UUU Programmable Logic Device Family March 1995, ver. 3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM devices based on secondgeneration Multiple Array MatriX MAX architecture
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max7000eepm7256e192-pin208-pin+3r12n10emp7032max7000
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EPX880-10
Abstract: altera epx740
Contextual Info: FLASHIogic Programmable Logic Device Family Features. • ■ Prelim inary Information ■ ■ ■ Formerly Intel's FLEXlogic iFX family High-performance programmable logic device (PLD) family SRAM-based logic w ith shadow EPROM or FLASH memory elements fabricated on 0.6- and 0.8-micron CMOS technology
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24v10epx88084-pin160-pin+5epx8160ds1s372208-pinepx880-10altera epx740
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EP1830
Abstract: EP1810 jedec 74HC EP1810 EP18302 EP1830 jedec
Contextual Info: EP1810 EPLDs High-Performance 48-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ Q General Description The EP1810 Erasable Programmable Logic Devices EPLDs offer LSI density,TTL-equivalentspeed, and low power consumption. Each EPLD can
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ep181048-macrocellep1830-20ep1830-25+6ep1830-30ep1830ep1810 jedec74hcep18302ep1830 jedec
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EP610
Abstract: Altera September 1991 EP610-20 acht30
Contextual Info: altera M7E D corp 05^5375 ODDgPbb T lg W ALT EP610 EPLDs High-Performance 16-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ □ □ General Description H igh-density replacem ent for TTL and 74HC w ith up to 600 gates
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ep61016-macrocellep630-20ep630-15+4ep630altera september 1991ep610-20acht30
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