DN74LS11 Search Results
DN74LS11 Functional Equivalents (3)
The Functional Equivalents tab will give you options that are likely to match the same function of DN74LS11, but it may not fit your design.
Always verify details of parts you are evaluating, as these parts are offered as suggestions for what you are looking for and are not guaranteed.
| Part Number | Manufacturer | Composite Price | Description |
|---|---|---|---|
| DM54LS15W | Rochester Electronics LLC | Check for Price | AND Gate, LS Series, 3-Func, 3-Input, TTL, CDFP14 |
| DM74LS11MX | Rochester Electronics LLC | Check for Price | AND Gate, LS Series, 3-Func, 3-Input, TTL, PDSO14 |
| 54LS15DMQB | Rochester Electronics LLC | Check for Price | AND Gate, LS Series, 3-Func, 3-Input, TTL, CDIP14 |
DN74LS11 Datasheets (16)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| DN74LS112D | Panasonic | Dual J-K Negative Edge Triggered Flip-Flops (with set and reset) | Scan | 90.2KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS112N | Panasonic | Dual J-K Negative Edge Triggered Flip-Flops (with Set and Reset) | Scan | 94.04KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS112P | Panasonic | Dual J-K Negative Edge Triggered Flip-Flops (with set and reset) | Scan | 90.2KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS112S | Panasonic | Dual J-K Negative Edge Triggered Flip-Flops (with Set and Reset) | Scan | 94.04KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS113D | Panasonic | Dual J-K Negative Edge-Triggered Flip-Flops (with set) | Scan | 82.24KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS113N | Panasonic | Dual J-K Negative Edge-Triggered Flip-Flops (with set) | Scan | 85.5KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS113P | Panasonic | Dual J-K Negative Edge-Triggered Flip-Flops (with set) | Scan | 82.24KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS113S | Panasonic | Dual J-K Negative Edge-Triggered Flip-Flops (with set) | Scan | 85.5KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS114D | Panasonic | Dual J-K Negative Edge Triggered Flip-Flops (with Set, Common Reset, and Common Clock) | Scan | 88.18KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS114N | Panasonic | Dual J-K Negative Edge Triggered Flip-Flops | Scan | 90.66KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS114P | Panasonic | Dual J-K Negative Edge Triggered Flip-Flops (with Set, Common Reset, and Common Clock) | Scan | 88.18KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS114S | Panasonic | Dual J-K Negative Edge Triggered Flip-Flops | Scan | 90.66KB | 3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS11N | Panasonic | Triple 3-Input Positive AND Gates | Scan | 47.74KB | 2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS11N | Panasonic | Triple 3-input Positive AND Gates | Scan | 45.24KB | 2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS11S | Panasonic | Triple 3-Input Positive AND Gates | Scan | 47.74KB | 2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| DN74LS11S | Panasonic | Triple 3-input Positive AND Gates | Scan | 45.24KB | 2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
DN74LS11 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
sr flip flop
Abstract: DN74LS113 MA161
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OCR Scan |
DN74LS DN74LS113 DN74LS113 14-pin S0-140) MA161. trS15ns, sr flip flop MA161 | |
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Contextual Info: LS TTL DN74LS Series DN74LS11 DN74LS11 D^74LS11 Triple 3-input P ositive AND Gates • Description P-1 D N 74L S 11 contains three 3-input positive isolation AND gate circuits. I Features • Low pow er consum ption P d = 13mW typical • High speed ( t pii = 9ns typical) |
OCR Scan |
DN74LS DN74LS11 DN74LS11 74LS11 14-pin SO-14D) MA161. | |
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Contextual Info: I LS TTL DN74LS Series DN74LS113 DN74LS113 Dual J-K Negative Edge-Triggered Flip-Flops with Set I Description P-1 DN74LS113 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals. |
OCR Scan |
DN74LS DN74LS113 DN74LS113 14-pin SO-14D) MA161. S15ns, | |
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Contextual Info: I LS TTL DN74LS Series DN74LS11 DN74LS11 T riple 3 -input P o sitiv e AND Gates • Description P-1 D N 7 4 L S 1 1 con tain s three 3-in put p ositive isolation A N D gate circuits. ■ Features • • • • L ow p o w er co n su m p tio n P d = 13mW ty p ica l |
OCR Scan |
DN74LSSÃ dN74LSii DN74LS11 14-pin SO-14D) DN74LS MA161. | |
DN74LS112
Abstract: MA161
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OCR Scan |
DN74LS DN74LS112 DN74LS112 16-ptn 16-pin S0-160) MA161 | |
DN74LS11
Abstract: MA161
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OCR Scan |
DN74LSSeries dN74LSii DN74LS11 DN74LS11 14-pin SO-14D) DN74LS MA161. MA161 | |
ma161Contextual Info: LS TTL DN74LS Series DN74LS112 DN74LS112 Dual J-K Negative Edge-Triggered F lip-F lops with S et and Reset • P-2 Description D N74LS112 contains two negative-edge triggered J-K flip flop circuits, each w ith independent clock-CP, J , K, and direct-coupled set and reset in p u t term inals. |
OCR Scan |
DN74LS DN74LS112 16-ptn 16-pin S0-160) ma161 | |
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Contextual Info: LS TTL DN74LS Series DN74LS114 DN74LS114 ivj'7q_ uSiiq- Dual J-K Negative Edge-Triggered F lip-F lops with Set,Common Reset and Common Clock • Description P-1 D N 74L S 1I4 contains tw o negative-edge triggered J-K flipflop circuits w ith com m on clock-CP and direct-coupled reset |
OCR Scan |
DN74LS DN74LS114 | |
DN74LS114
Abstract: MA161
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OCR Scan |
DN74LS DN74LS114 DN74LS114 14-pin SO-14D) MA161 | |
DN74LS112
Abstract: MA161
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OCR Scan |
DN74LS DN74LS112 DN74LS112 16-pm 16-pin SO-16D) MA161 | |
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Contextual Info: I DN74LS11 L S T T L DN74LS Series DN74LS11 Triple 3 -input P ositive AND Gates P-1 • Description D N 7 4 L S 1 1 c o n ta in s th re e 3 -in p u t p o sitiv e is o la tio n A N D gate circ u its. ■ Features • L ow p o w e r c o n s u m p tio n P d = 13m W ty p ic a l |
OCR Scan |
DN74LS DN74LS11 14-pin SO-14D) | |
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Contextual Info: LS TTL DN74LS Series D N 7 4 LS1 1 2 DN74LS112 i0 7 ^ IS ¡ ¡ ^ Dual J-K Negative Edge-Triggered Flip-Flops with Set and Reset H Description P -2 DN 74LS112 contains two negative-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and |
OCR Scan |
DN74LS DN74LS112 74LS112 | |
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Contextual Info: LS TTL DN74LS Series DN74LS114 DN74LS114 Dual J-K Negative Edge-Triggered F lip-F lops with Set, Common Reset and Common Clock • Description DN74LS114 contains two negative-edge triggered J-K flipflop circuits with common clock-CP and direct-coupled reset |
OCR Scan |
DN74LS DN74LS114 DN74LS114 | |
400M
Abstract: DN74LS114 MA161
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OCR Scan |
DN74LS DN74LS114 DN74LS114 M74-LSuq- DN74LS1I4 14-pin SO-14D) 400M MA161 | |
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DN74LS113
Abstract: MA161 100 mhz trigger generator 0n74
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OCR Scan |
0N74LS DN74LS113 DN74LS113 14-pin SO-14D) trS15ns. MA161 100 mhz trigger generator 0n74 | |
JK flip flop ICContextual Info: LS TTL DN74LS Series DN74LS113 DN74LS113 l^7^iS 3 Dual J-K Negative Edge-Triggered Flip-Flops with Set) • Description DN74LS113 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set input terminals. |
OCR Scan |
DN74LS DN74LS113 DN74LS113 14-pin SO-14D) MA161. JK flip flop IC | |
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Contextual Info: LS TTL DN74LS Series DN74LS112 D N 7 4 L S 1 1 2 Dual J-K Negative Edge-Triggered Flip-Flops with Set and Reset • Description P-2 DN74LS112 contains two negative-edge triggered J-K flipflop circuits, each with independent clock-CP, J, K, and direct-coupled set and reset input terminals. |
OCR Scan |
DN74LS DN74LS112 DN74LS112 16-pin | |
an6512n
Abstract: mn1225 MN1280 mn6520 MN6130 MN1201A MN6147C MN12C261D MN12C201D MN3107
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OCR Scan |
MN115P MN116P MN1201A MN1201M MN1201S MN1202M MN1204A MN1204B MN1204E MN1204F an6512n mn1225 MN1280 mn6520 MN6130 MN6147C MN12C261D MN12C201D MN3107 | |
MN1280
Abstract: AN6512 MN15814 MN15245 2Sb1163a mn158413 AN7210 AN7226 MN15287 MN15283
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OCR Scan |
MN1380 MN13801 MN13802 MN1381 MN13811 MN13812 MN1382 MN13821 MN13822 MN1544 MN1280 AN6512 MN15814 MN15245 2Sb1163a mn158413 AN7210 AN7226 MN15287 MN15283 | |
MN1873287
Abstract: an6512n 2sk3190 MN171202 mn158413 mn15142 mn187164 mn6740 AN7210 MN15283
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Original |
MN101C01C MN15224 MN101C01D MN15226 MN101C027 MN15261 MN101C03A MN101C38A MN15263 MN101C06D MN1873287 an6512n 2sk3190 MN171202 mn158413 mn15142 mn187164 mn6740 AN7210 MN15283 | |