CY7C1327 Search Results

CY7C1327B

Contextual Info: 327 CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

CY7C1327G

Abstract: CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI
Contextual Info: CY7C1327G PRELIMINARY 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1327 256K X 18 Synchronous-Pipelined Cache RAM Features The CY7C1327 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states

Contextual Info: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1327G PRELIMINARY 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times

AN54908

Abstract: CY7C1327G
Contextual Info: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description The CY7C1327G SRAM[1] integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are

99503

Abstract: 8361H CY7C1339B CY7C1325B CY7C1327B CY7C1329 CY7C1338B CY7C1345B CY7C1347B 619911-1
Contextual Info: Cypress Semiconductor Product Qualification Report QTP# 99503VERSION 2.0 October, 2000 4 Meg Synchronous Cache RAM R52D-3 Technology at Fab 4 CY7C1325B 256K x 18 Synchronous Flow-Through Cache RAM CY7C1327B 256K x 18 Synchronous Pipelined Cache RAM CY7C1345B

Contextual Info: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

Contextual Info: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

Contextual Info: 327A CY7C1327A/GVT71256G18 256K x 18 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • eral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

Contextual Info: 327 CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

Contextual Info: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

CY7C1327G

Contextual Info: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply (VDD) • 2.5V I/O power supply (VDDQ) • Fast clock-to-output times

CY7C1327G

Contextual Info: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Features Functional Description • Registered Inputs and Outputs for Pipelined Operation ■ 256K x18 common I/O Architecture ■ 3.3V Core Power Supply (VDD) ■ 2.5V I/O Power Supply (VDDQ) ■ Fast Clock-to-Output Times

CY7C1327B

Contextual Info: CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

CY7C1327-133AC

Abstract: CY7C1327
Contextual Info: CY7C1327 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327 I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

intel core i7

Abstract: intel quad core i7 CY7C1327 CY7C1327-166AC
Contextual Info: fax id: 1107 CYPRESS CY7C1327 P R E L IM IN A R Y 256K X 18 Synchronous-Pipelined Cache RAM Features Functional Description Low 1.65 m W s ta n d b y p o w er (f= 0, L ve rs io n ) S u p p o rts 10 0-M H z bus fo r P en tiu m and Pow erPC o p e ratio n s w ith zero w ait sta tes

Contextual Info: CY7C1327G 4-Mbit 256 K x 18 Pipelined Sync SRAM 4-Mbit (256 K × 18) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1327G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

Contextual Info: PRELIMINARY CY7C1327F 256K x 18 Synchronous Pipelined Static RAM Features The CY7C1327F I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Fully registered inputs and outputs for pipelined operation

CY7C1327G

Contextual Info: CY7C1327G 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply (VDD) • 2.5V I/O power supply (VDDQ) • Fast clock-to-output times

Contextual Info: PRELIMINARY CY7C1327F 256K x 18 Synchronous Pipelined Static RAM Features The CY7C1327F I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Fully registered inputs and outputs for pipelined operation

CY7C1327F

Abstract: CY7C1327F-225AC CY7C1327F-225BGC CY7C1327F-250AC CY7C1327F-250AI CY7C1327F-250BGC CY7C1327F-250BGI
Contextual Info: CY7C1327F 4-Mb 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1327AL 256K x 18 Synchronous Pipelined Burst SRAM The CY7C1327AL SRAM integrates 262,144x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered

CY7C1327F

Abstract: CY7C1327F-225AC CY7C1327F-225BGC CY7C1327F-250AC CY7C1327F-250AI CY7C1327F-250BGC CY7C1327F-250BGI
Contextual Info: CY7C1327F 4-Mb 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times