CY7C1292DV18 Search Results
CY7C1292DV18 Datasheets (2)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| CY7C1292DV18 | 
 
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9-Mbit QDR- II SRAM 2-Word Burst Architecture | Original | 1MB | 23 | ||
| CY7C1292DV18-167BZC | 
 
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9-Mbit QDR- II SRAM 2-Word Burst Architecture | Original | 1MB | 23 | 
CY7C1292DV18 Price and Stock
Infineon Technologies AG CY7C1292DV18-167BZCIC SRAM 9MBIT PAR 167MHZ 165FBGA | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CY7C1292DV18-167BZC | Tray | 136 | 
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Rochester Electronics LLC CY7C1292DV18-167BZCIC SRAM 9MBIT PAR 167MHZ 165FBGA | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CY7C1292DV18-167BZC | Tray | 11 | 
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Cypress Semiconductor CY7C1292DV18-167BZCCY7C1292DV18-167BZC | 
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
 
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CY7C1292DV18-167BZC | 100 | 25 | 
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Buy Now | ||||||
 
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CY7C1292DV18-167BZC | 100 | 1 | 
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CY7C1292DV18 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
CY7C1292DV18
Abstract: CY7C1294DV18 
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 Original  | 
CY7C1292DV18 CY7C1294DV18 CY7C1292DV18 CY7C1294DV18 | |
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 Contextual Info: CY7C1292DV18 CY7C1294DV18 PRELIMINARY 9-Mbit QDR-II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth • 2-Word Burst on all accesses  | 
 Original  | 
CY7C1292DV18 CY7C1294DV18 300-MHz CY7C1292DV18/CY7C1294DV18 | |
CY7C1292DV18
Abstract: CY7C1294DV18 
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 Original  | 
CY7C1292DV18 CY7C1294DV18 CY7C1292DV18 CY7C1294DV18 | |
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 Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-00350 Spec Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR II SRAM 2-Word Burst Architecture Sunset Owner: AJU Replaced By: None CY7C1292DV18 CY7C1294DV18 9-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations  | 
 Original  | 
CY7C1292DV18/CY7C1294DV18 CY7C1292DV18 CY7C1294DV18 | |
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 Contextual Info: CY7C1292DV18 CY7C1294DV18 9-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1292DV18 – 512K x 18 CY7C1294DV18 – 256K x 36 ■ 250 MHz clock for high bandwidth  | 
 Original  | 
CY7C1292DV18 CY7C1294DV18 CY7C1292DV18 | |
BV25
Abstract: CY7C129 CY7C130 CY7C131 CY7C132 EV25 ev18 
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 Original  | 
CY7C129 DV18/CY7C130 CY7C130 BV18/CY7C130 BV25/CY7C132 CY7C131 CY7C132 BV18/CY7C139 CY7C191 BV18/CY7C141 BV25 EV25 ev18 | |
05564
Abstract: BV25 CY7C129 CY7C130 CY7C131 CY7C132 CY7C1422AV18 1428A 
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 Original  | 
CY7C129 DV18/CY7C130 CY7C130 BV18/CY7C130 BV25/CY7C132 CY7C131 CY7C132 BV18/CY7C139 CY7C191 BV18/CY7C141 05564 BV25 CY7C1422AV18 1428A |