C502A Search Results

Contextual Info: PLL620-80 Low Phase Noise XO 9.5-65MHz Output DIE CONFIGURATION FEATURES XIN OUTSEL0^ VDD VDD VDD VDD N/C Reserved OUTSEL1^ 24 23 22 21 20 19 18 17 26 Die ID: A2020-20B XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF

5N521

Contextual Info: 1 PLL620-20 1 Low Phase Noise XO for HF Fund. and 3 rd O.T. DIE CONFIGURATION FEATURES XIN DESCRIPTION VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 26 Die ID: A1212-12 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 C502A 3 4 5 6 7 8 GND GND GND Reserved

A1010

Abstract: C502A PLL620-00DC
Contextual Info: PLL620-00 Low Phase Noise XO with multipliers for HF Fund. and 3 rd O.T. DIE SPECIFICATIONS 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 NC 31 VDD SEL0^ SEL1^ OUTSEL1^ VDD XOUT VDD VDD 26 21 20 19 18 17 Die ID: A1010-10A C502A 3 4 5 6 7 8 GNDBUF (0,0) 2 GND Y X Name

oT 408

Abstract: PL620-21
Contextual Info: PL620-21 Low Phase Noise XO for HF Fund. and 3 rd O.T. DIE CONFIGURATION XIN VDD VDD VDD VDD DNC Reserved Reserved 24 23 22 21 20 19 18 XOUT 27 DNC 28 DNC 29 OE_CTRL 30 DNC 31 Die ID: A1919-19C C502A 3 4 5 6 GND Reserved X 7 8 GNDBUF 2 GNDBUF 1 GND (0,0)

a2020

Abstract: C502A E5500 P620-80DC PLL620-80 PLL620-80DC
Contextual Info: PLL620-80 Low Phase Noise XO 9.5-65MHz Output DIE CONFIGURATION FEATURES XIN OUTSEL0^ VDD VDD VDD VDD N/C Reserved OUTSEL1^ 24 23 22 21 20 19 18 17 26 Die ID: A2020-20B XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF

precision shunt regulators 431

Abstract: TL4313 TL431A TL431B TL431C
Contextual Info: CYStech Electronics Corp. Spec. No. : C502A3 Issued Date : 2003.03.26 Revised Date : 2007.12.21 Page No. : 1/6 Adjustable Precision Shunt Regulators TL431A3 Description TO-92 The TL431A3 series are three-terminal adjustable regulators with guaranteed thermal stability over applicable temperature ranges. The output voltage may be set to any

C502A

Abstract: TL431A TL431B TL431C precision shunt regulators 431 Cystek
Contextual Info: CYStech Electronics Corp. Spec. No. : C502A3 Issued Date : 2003.03.26 Revised Date : 2008.10.09 Page No. : 1/6 Adjustable Precision Shunt Regulators TL431A3 Description TO-92 The TL431A3 series are three-terminal adjustable regulators with guaranteed thermal stability over applicable temperature ranges. The output voltage may be set to any

precision shunt regulators 431

Abstract: TL431XA3 TL431 TL431A TL431B TL431C
Contextual Info: CYStech Electronics Corp. Spec. No. : C502A3 Issued Date : 2003.03.26 Revised Date : 2005.06.29 Page No. : 1/6 Adjustable Precision Shunt Regulators TL431XA3 Description The TL431 series are three-terminal adjustable regulators with guaranteed TO-92 thermal stability over applicable temperature ranges. The output voltage

Contextual Info: PL520-20 Low Phase Noise VCXO for 100-200MHz Fundamental Crystals DIE CONFIGURATION FEATURES XIN VDD VDD VDD VDD DNC DNC OUTSEL1 25 24 23 22 21 20 19 18 26 Die ID: A1919-19B XOUT 27 DNC 28 DNC 29 OE 30 VCON 31 DESCRIPTION C502A BLOCK DIAGRAM OE Q VCON Oscillator

Contextual Info: PLL520-00 Low Phase Noise VCXO with multipliers for 100-200MHz Fund Xtal FEATURES OUTSEL0^ VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 23 22 21 20 19 18 17 26 Die ID: A1919-19A XOUT 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 VCON 31 C502A 16 CMOS 15 LVDSB 14 PECLB 13 12 VDDBUF

LM587

Abstract: lm 587 C502A P580-30DC PL580-30 PL580-30DC
Contextual Info: Preliminary 38MHz to 640MHz Low Phase Noise VCXO FEATURES OUTSEL0v VDDOSC VDDANA VDDANA VDDDIG SEL0^ SEL1^ OUTSEL1^ 23 22 21 20 19 18 XIN 26 XOUT 27 SEL2 28 DNC 29 Die ID: 2525-25 30 VCON 31 1 2 3 4 5 6 7 8 LP LM DNC DNC GNDDIG GNDBUF C502A (0,0) X The PL580-30 is a monolithic low jitter and low phase

C502A

Abstract: PLL620-20DC crystal ot 20 MHz
Contextual Info: PLL620-20 Low Phase Noise XO for HF Fund. and 3 rd O.T. DIE CONFIGURATION FEATURES XIN 26 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 VDD N/C Reserved Reserved 23 VDD VDD 24 22 21 20 19 18 Die ID: A1212-12 C502A 3 4 5 6 7 8 GND GND Reserved GNDBUF GNDBUF (0,0)

XTAL 25MHZ Datasheet

Abstract: C502A P502-30DC PLL502-30 PLL502-30DC OSC 25MHz 3.3V a2828
Contextual Info: 750kHz – 800MHz Low Phase Noise VCXO for 12 to 25MHz Crystals XIN 26 XOUT 27 SEL3^ 28 SEL2^ 29 OE_CTRL 30 VCON 31 VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 24 23 22 21 20 19 18 Die ID: A2828-28 1 2 3 4 5 6 7 GND GND GND N/C GND C502A Note: ^ denotes internal pull up

454 marking CA 8

Abstract: a2020 C502A P620-30DC PLL620-30 PLL620-30DC
Contextual Info: PLL620-30 PECL and LVDS Low Phase Noise XO 32.5 to 130MHz output DIE CONFIGURATION FEATURES DIE SPECIFICATIONS XIN 26 XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 N/C Reserved Reserved 21 20 19 18 17 Die ID: A2020-20A C502A 5 GND 6 X 7 8 GNDBUF 4 GNDBUF 3 Reserved

C502A

Abstract: PLL520-20 clock ma 1042
Contextual Info: PLL520-20 Low Phase Noise VCXO for 100-200MHz Fundamental Crystals FEATURES DIE CONFIGURATION XIN VDD VDD VDD VDD DNC DNC OUTSEL1 (1550,1475) 25 24 23 22 21 20 19 18 17 26 Die ID: A1919-19B XOUT 27 DNC 28 DNC 29 OE 30 VCON 31 DESCRIPTION C502A BLOCK DIAGRAM

Contextual Info: PL520-00 Low Phase Noise VCXO with multipliers for 100 -200MHz Fund Xtal FEATURES OUTSEL0^ VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 24 23 22 21 20 19 18 Die ID: A1919-19A XOUT 27 SEL3^ 28 SEL2^ 29 OE CTRL 30 VCON 31 C502A 17 GNDBUF 16 CMOS 15 LVDSB 14 PECLB

a2020

Contextual Info: PL620-30 PECL and LVDS Low Phase Noise XO 32.5 to 130MHz output DIE CONFIGURATION FEATURES XIN DIE SPECIFICATIONS VDD VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 17 26 Die ID: A2020-20A XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A Value Size

C502A

Abstract: PLL620-20DC
Contextual Info: PLL620-20 Low Phase Noise XO for HF Fund. and 3 rd O.T. DIE CONFIGURATION FEATURES XIN VDD VDD VDD N/C Reserved Reserved 24 23 22 21 20 19 18 26 Die ID: A1212-12 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 C502A 3 4 5 6 7 8 GND GND Reserved GNDBUF GNDBUF (0,0)

clock ma 1042

Abstract: C502A PLL620-20DC P620
Contextual Info: PLL620-20 Low Phase Noise XO for HF Fund. and 3 rd O.T. FEATURES DIE CONFIGURATION 65 mil XIN VDD VDD VDD VDD N/C Reserved Reserved 24 23 22 21 20 19 18 26 Die ID: A1212-12 XOUT 27 N/C 28 N/C 29 OE CTRL 30 N/C 31 C502A 3 4 5 6 7 8 GND GND Reserved GNDBUF

P620-21DC

Abstract: C502A PLL620-21 PLL620-21DC
Contextual Info: PLL620-21 Low Phase Noise XO for HF Fund. and 3 rd O.T. VDD VDD VDD VDD DNC Reserved Reserved 24 23 22 21 20 19 18 26 XIN XOUT 27 DNC 28 DNC 29 OE_CTRL 30 DNC 31 Die ID: A1919-19C C502A 3 4 5 6 GND Reserved X 7 8 GNDBUF 2 GNDBUF 1 GND (0,0) Y (1550,1475)

a2020

Abstract: clock ma 1042 C502A P620-30DC PLL620-30 PLL620-30DC
Contextual Info: PLL620-30 PECL and LVDS Low Phase Noise XO 32.5 to 130MHz output DIE CONFIGURATION FEATURES XIN DIE SPECIFICATIONS VDD VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 17 26 Die ID: A2020-20A XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A 5 Value

Contextual Info: PL620-30 PECL and LVDS Low Phase Noise XO 32.5 to 130MHz output DIE CONFIGURATION FEATURES XIN DIE SPECIFICATIONS VDD VDD VDD VDD N/C Reserved Reserved 25 24 23 22 21 20 19 18 17 26 Die ID: A2020-20A XOUT 27 N/C 28 S2^ 29 OE CTRL 30 N/C 31 C502A Value Size

C502A

Abstract: PLL520-20 VARICAPS
Contextual Info: PLL520-20 Preliminary Low Phase Noise VCXO for 100-200MHz Fundamental Crystals FEATURES DIE CONFIGURATION 62 mil XIN VDD VDD VDD N/C DNC DNC 23 22 21 20 19 18 17 XOUT 27 DNC 28 DNC 29 OE CTRL 30 VCON 31 Die ID: A1919-19B C502A 4 5 6 GND Reserved X 7 8 GNDBUF

Contextual Info: PLL520-80 Low Phase Noise VCXO 9.5-65MHz DIE CONFIGURATION FEATURES XIN DIE SPECIFICATIONS Name Value Size Reverse side Pad dimensions Thickness 62 x 65 mil GND 80 micron x 80 micron 10 mil OUTSEL0^ VDD VDD VDD VDD N/C Reserved OUTSEL1^ 24 23 22 21 20 19