AM2962 Search Results

Contextual Info: Am2961/Am2962 Am2961 / Am2962 4-Bit Error Correction Multiple Bus Buffers DISTINCTIVE CHARACTERISTICS Inverting data bus for Am2961 and noninverting for Am2962 Data bus latches allow operation with multiplexed buses Space saving 24-pin 0.3* package Provides complete data path interface between the

Contextual Info: Am2961/Am2962 A m 2961/A m 2962 4-B it Error Correction M ultiple Bus Buffers DISTINCTIVE CHARACTERISTICS Provides complete data path interface between the Am2960 Error Detection and Correction Unit, the sys­ tem data bus and dynamic RAM memory Three-state 24mA output to data bus

Am2960 applications note

Abstract: RAM circuit diagram
Contextual Info: Am2961/Am2962 A m 2961/A m 2962 4-B it Error Correction M ultiple Bus Buffers DISTINCTIVE CHARACTERISTICS Provides complete data path interface between the Am2960 Error Detection and Correction Unit, the sys­ tem data bus and dynamic RAM memory Three-state 24mA output to data bus

m2961

Abstract: Am2961/2962
Contextual Info: 396 Z U IV /1 96 Z U IV Am2961/Am2962 4-Bit Error Correction Multiple Bus Buffers DISTINCTIVE CHARACTERISTICS Provides complete data path interface between the Am2960 Error Detection and Correction Unit, the sys­ tem data bus and dynamic RAM memory Three-state 24mA output to data bus

Error Correction

Abstract: Bus Buffers AM2960
Contextual Info: Am2961 • Am2962 4-Bit Error Correction Multiple Bus Buffers DISTINCTIVE CHARACTERISTICS FUNCTIONAL DESCRIPTION • Quad high-speed LSI bus-transceiver • Provides complete data path interface between the Am2960 Error Detection and Correction Unit, the system data bus and

AmZ8000

Abstract: CD0018
Contextual Info: Am8127 AmZ8000 Clock Generator DISTINCTIVE CHARACTERISTICS High-drlve high-level clock output Special output provides clock signal matched to re­ quirements of AmZBOOO* CPU 4MHz and some 6 MHz applications , MMU and DMA devices. Synchronized WAIT state and time-out controls

2B0365

Abstract: 74ls244 latch ic Z8127 z80 multibus Am286
Contextual Info: Am8163/Am8167 A m 816 3 /A m 816 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS • Complete CPU to dynamic RAM control interface • R A S /M S E L/C A S Sequencer to eliminate delay lines • Complete EDC/data path controls for W ord/Byte read

Contextual Info: Am8163/Am8167 Am8163/Am8167 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS • • • • Complete CPU to dynamic RAM control Interface RAS/MSEL/óÀS Sequencer to eliminate delay lines Complete EDC/data path controls for Word/Byte read

29828A

Contextual Info: Am29827A/Am29828A Am29827A/Am29828A High-Performance Buffers DISTIN CTIVE C H A R A C T E R IS T IC S • High-speed buffers and inverters - tpo = 5.0 ns Typical • 200-m V minimum input hysteresis on input data ports • Three-state outputs glitch-free during power-up and

Contextual Info: Am2960/Am2960-1 /Am2960A Advanced Micro Devices Cascadable 16-Bit Error Detection and Correction Unit DISTINCTIVE CHARACTERISTICS Boosts Memory Reliability Corrects all single-bit errors. Detects all double and some triple-bit errors. Very High Speed Perfect for MOS microprocessor, minicomputer, and

LEI-4

Abstract: Am29000 am2971 AM2969 MC01 Am29C60
Contextual Info: Am2969 M e m o ry T im in g C o n tro lle r w ith E D C T im in g C on trol P R E L IM IN A R Y > 3 DISTINCTIVE CHARACTERISTICS Refresh control: internal o r external O n-chip interval tim er for a utom atic refresh S ynchrono us or a s y n ch ro n o u s arb itration of

cq 721

Abstract: am26ls31 27LS00 TRANSISTOR SUBSTITUTION Amdasm am2911pc 25S558 STK 025 power amplifier GE semiconductor data handbook am29811adc-b
Contextual Info: í i í i í i n z ta a a a a a a a a a a a r n a a a a a a a a a a a a a i: 33a a a a a a n a a a a a ; a a a a a a a a n a a iia a r r ia a a a a a n a a iia a a r l a n g a s í i í i í i * i¿ w n r w a s a jn sü n n a n a n n n n íiíi íiíiíi n n s n n n

Contextual Info: Am8127 AmZ8000 Clock Generator DISTINCTIVE CHARACTERISTICS Hlgh-drive high-level clock output Four TTL-level clocks Special output provides clock signal matched to re­ quirements of AmZSOOO* CPU 4MHz and some 6 MHz applications , MMU and DMA devices. Generates synchronized TTL compatible clocks at

MAX2852

Abstract: AM2960
Contextual Info: Am2960/Am2960-1 /Am2960A Advanced Micro Devices Cascadable 16-Bit Error Detection and Correction Unit DISTINCTIVE CHARACTERISTICS Boosts Memory Reliability Corrects all single-bit errors. Detects all double and some triple-bit errors. Very High Speed Perfect or MOS microprocessor, minicomputer, and

MPR-502

Abstract: 9016dpc AM2960DC
Contextual Info: a ? P # >* V>?V Ä ^ -0 ° ' \G ° h P r# O <g> -s O r ,o O A <$• K 0< ^ P - rO N * J§ > . <<& '" * ^ & ^ *ä *w nnnnnnnnnnnnnnnnnnnnnnnn nnnnnnnnnnnnnnnnnnnnnnnn nnnnnnnnnnnnnnnnnnnnnnnn nnnnnnnnnnnnnnnnnnnnnnnn CIil nn nei nn nn nn nn nn nn nn nn nn

AM2982 7 DC

Abstract: am29827
Contextual Info: Am29827/Am29828 Am29827/Am29828 High Performance Buffers DISTINCTIVE CHARACTERISTICS High-speed buffers and inverters - Noninverting tpo “ 5.0ns typ - Inverting tpo - 4.5ns typ 200mV minimum input hysteresis on input data ports • Three-state outputs glitch-free during power-up and

str f 6167

Abstract: amz8127 str 6167 supi 3 ls z80b Am8001 AM8163 IC HS 8167 z80 multibus 74LS240
Contextual Info: Am8163/Am8167 A m 8 1 6 3 /A m 8 1 6 7 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

AM29925APC

Contextual Info: Am29821A/Am29823A/Am29825A Am29921A/Am29923A/Am29925A Am29821A/Am29823A/Am29825A Am29921A/Am29923A/Am29925A High-Performance Bus Interface Registers DISTINCTIVE CHARACTERISTICS • High-speed parallel positive edge-triggered registers with D-type flip-flops

AMZ8000

Abstract: DF000380 AmZ8001/AmZ8002
Contextual Info: Am8127 Am8127 Am Z8000 C lo c k G e n e ra to r DISTINCTIVE CHARACTERISTICS High-drlve high-level clock output Special output provides clock signal matched to re­ quirements of AmZ8000* CPU 4MHz and some 6MHz applications , M MU and DMA devices. Synchronized WAIT state and time-out controls

74LS189 equivalent

Abstract: 74LS200 AmZ8036 Z8104 74LS300 AM9511 Am2505 27s13 54S244 27LS00
Contextual Info: Advanced Micro Devices Condensed Catalog 1981 Advanced Micro Devices, Inc. Advanced Micro Devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The company assumes no responsibility for the use of any circuits described herein.

triac tag 8518

Abstract: 70146 DS3654 X2864AD 7 segment display RL S5220 TC9160 la 4440 amplifier circuit diagram 300 watt philips ecg master replacement guide vtl 3829 A-C4 TCA965 equivalent
Contextual Info: 1985 0 / 0 / CONTENTS VOLUME I Introduction to IC MASTER 3 Advertisers’ Index 8 Master Selection Guide Function Index I0 Part Number Index 40 Part Number Guide 300 Logo Guide 346 Application Note Directory 349 Military Parts Directory 50I Testing 506 Cross Reference

TV THOMPSON 29 DF 170 G

Abstract: STK 1000 watt power amp circuit diagram ERO Electronic F-48 AM9016E am29203 "evaluation board" 29ls18pc free stk ic sram book 27S28 free transistor equivalent book 2sc
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AM29824

Abstract: AM29821 Am29820
Contextual Info: Am29821 - 26 Am29821 - 26 High Performance Bus Interface Registers DISTINCTIVE CHARACTERISTICS High-speed parallel registers with positive edge-trig­ gered D-type flip-flops - Noninverting CP-Y tpQ - 7.5ns typ - Inverting CP-Y tpo ” 7.5ns typ Buffered common Clock Enable PR and asynchronous

pinout AM2 AMD processor

Abstract: spf 9001 IC 4558 CIRCUIT DIAGRAM AM2969 4558 diagram application data sheet ic 4558 80386 microprocessor pin out diagram amd am2 pinout ic 4558 pin diagram pin diagram of amd am2 processor
Contextual Info: Am2969 S Memory Timing Controller with EDC Timing Control PRELIMINARY > 3 ro D IS T IN C T IV E C H A R A C T E R IS T IC S Refresh control: internal or external On-chip interval timer for automatic refresh Synchronous or asynchronous arbitration of memory cycles