AS7C4096 Search Results

AS7C4096-15JI

Abstract: AS7C34096 AS7C4096 AS7C34096-12TI
Contextual Info: October 2001 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • Low power consumption: STANDBY • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins

AS7C4096A

Abstract: AS7C4096A-20JI AS7C4096A-20TI AS7C4096 AS7C4096A-10JC AS7C4096A-10JI AS7C4096A-10TC AS7C4096A-10TI AS7C4096A-12JC AS7C4096A-12JI
Contextual Info: February 2006 AS7C4096A 5.0V 512K x 8 CMOS SRAM • Equal access and cycle times • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages Features • Pin compatible to AS7C4096 • Industrial and commercial temperature

Contextual Info: AS7C4096 AS7C34096 A 5V/3.3V 512Kx8 CMOS SRAM Features • Organization: 262,144 words x 16 bits • High speed - 12/15/ 20/ 25 ns address access time - 5/ 5/ 617 ns output enable access time • Law power consumption - .Active: 990 mW max 20 ns cycle, 5V

as7c4096a-15jc

Contextual Info: November 2004 Preliminary AS7C4096A 5.0V 512K x 8 CMOS SRAM • Equal access and cycle times • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages Features • Pin compatible to AS7C4096 • Industrial and commercial temperature

AS7C4096-20JI

Abstract: AS7C34096-12TI
Contextual Info: January 2001 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins • High speed

AS7C34096

Abstract: AS7C4096 AS7C4096-20JI AS7C34096-12TI
Contextual Info: March 2002 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • Low power consumption: STANDBY • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins

7C4096

Abstract: AS7C34096 AS7C4096 5hbs AA344
Contextual Info: H igh Perform ance S12KX8 CMOS SRAM AS7C4096 A S7C 34096 1 5 1 2 K X 8 C M O S SR A M P relim inary inform ation SRAM Features • O rg a n iz a tio n : 5 2 4 ,2 8 8 w o rd s x 8 bits • H ig h sp e ed Easy m e m o ry e x p a n s io n w ith CE, OE in p u ts

AS7C4096-12TC

Abstract: AS7C4096-20JI AS7C34096-12TI
Contextual Info: December 2001 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • Low power consumption: STANDBY • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins

Contextual Info: September 2001 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • Low power consumption: STANDBY • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins

AS7C4096

Abstract: AS7C4096A AS7C4096A-10JC AS7C4096A-10JI AS7C4096A-10TC AS7C4096A-10TI AS7C4096A-12JC AS7C4096A-12JI AS7C4096A-12TC
Contextual Info: May 2005 Preliminary AS7C4096A 5.0V 512K x 8 CMOS SRAM • Equal access and cycle times • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages Features • Pin compatible to AS7C4096 • Industrial and commercial temperature

Contextual Info: H igh Perform ance 512K X8 CMOS SRAM n II AS7C4096 A S7C 34096 5 1 2 K X 8 C M O S SR A M Preliminary information 1 E asy m e m o r y e x p a n s io n w i t h CE, O E i n p u ts Logic block diagram Pin arrangement SRAM Features • Organization: 524,288 words x 8 bits

Contextual Info: H igh P e r fo r m a n c e •■ AS7C4096 AS7C34096 A 512KX8 H CM O S SRAM 5 I 2 K X 8 C M O S SR A M Features • O rgan ization : 5 2 4 ,2 8 8 w o rd s x 8 bits • 3 6 -p in JEDEC stan dard pack ages • H igh speed - 4 0 0 m il T SO P II - 5 / S / 6 / 7 n s o u tp u t enable access tim e

AS7C34096-25JC

Contextual Info: AS7C4096 AS7C34096 5V/3.3V 512Kx8 CMOS SRAM Features • Organization: 524,288 w ords x 8 bits • High speed - 1 2 /1 5 /2 0 /2 5 ns address access time - 5 / 5 / 6 / 7 ns output enable access time • Low power consumption - Active: 990 m W max 20 ns cycle, 5V

AS7C4096-20JI

Abstract: AS7C34096 AS7C4096 as7c4096-15ji AS7C34096-12TI
Contextual Info: March 2002 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • Low power consumption: STANDBY • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins

Contextual Info: JULY 2000 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • Low power consumption: STANDBY - 110 mW AS7C4096 / max CMOS - 72 mW (AS7C34096) / max CMOS • AS7C4096 (5V version) • AS7C34096 (3.3V version) • Industrial and commercial temperature

Contextual Info: February 2006 AS7C4096A 5.0V 512K x 8 CMOS SRAM • Equal access and cycle times • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packages Features • Pin compatible to AS7C4096 • Industrial and commercial temperature

4342414

Abstract: AS7C34096 AS7C34096-10JC AS7C34096-10TC AS7C34096-12JC AS7C4096 AS7C4096-12JC AS7C4096-12JI AS7C4096-15JC AS7C4096-20JC
Contextual Info: January 2005 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • Low power consumption: STANDBY • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins

datasheet CI 556

Abstract: AS7C34096 AS7C4096
Contextual Info: High Performance 512Kx8 CMOS SRAM AS7C4096 AS7C34096 512K×8 CMOS SRAM Preliminary information Features • Organization: 524,288 words × 8 bits • High speed - 12/15/20/25 ns address access time - 6/7/8/9 ns output enable access time • Low power consumption

AS7C34096

Abstract: AS7C4096 AS7C4096-20JI AS7C34096-12TI
Contextual Info: March 2001 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins • High speed

AS7C4096-20JI

Abstract: AS7C34096-12TI
Contextual Info: $SULO#5333# $6:&73<9 $6:&673<9 8926169#845.ð;#&026#65$0 HDWXUHV • Low power consumption: STANDBY - 55 mW AS7C4096) / max CMOS - 36 mW (AS7C34096) / max CMOS • 2.0V data retention • Equal access and cycle times • Easy memory expansion with CE, OE inputs

AS7C34096

Abstract: AS7C34096-10JC AS7C34096-10TC AS7C4096 AS7C4096-20JI AS7C34096-12TI
Contextual Info: July 2001 AS7C4096 AS7C34096 5V/3.3V 512K x 8 CMOS SRAM Features • AS7C4096 5V version • AS7C34096 (3.3V version) • Industrial and commercial temperature • Organization: 524,288 words × 8 bits • Center power and ground pins • High speed

CS16LV40963

Abstract: BS62LV4006 sram cross reference CS18LV40963 LY6264 Hynix Cross Reference cs18lv10245 cs18lv02560 LY621024 K6X1008C2D
Contextual Info: www.ashlea.co.uk 01793 783784 Low power SRAM Cross Reference Density Configuration 64K 8Kx8 256K 32Kx8 Lyontek LY6264 LY62L64 LY62256 LY62L256 LY62256 2.7-5.5 1M 128Kx8 64Kx16 LY621024 LY62L1024 LY62L6416 Samsung K6X0808C1D K6X0808T1D K6X1008C2D K6X1008T2D

AS7C34096

Abstract: AS7C4096 AS7C34096-12JT 7C4096 LT2000
Contextual Info: AS7C4 096 AS7C34 09Ó 5V/3.3V 512Kx8 CMOS SRAM Features • O rganization: 524,2 8 8 w ords x 8 bits • H igh speed - 1 2 /1 5 /2 0 / 2 5 ns address access tim e - 5 / 5 / 6 / 7 ns o u tp u t enable access tim e • Low pow er consum ption - Active: 990 m W m ax 20 ns cycle, 5V

1H08S

Abstract: PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR
Contextual Info: Supervisors Cross Reference Guide Alliance Maxim/Dallas IMP ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA DS1232LP IMP1232LPEMA ASM1232LPN DS1232LP IMP1232LPN Analog Devices Micrel Microchip MIC1232N TC1232CPA - - - - - -