APRIL1993 Search Results

SCAS142A-D3791

Abstract: TTL Schmitt-Trigger Inverters six independent Schmitt-trigger inverters 74ACT11014
Contextual Info: 74ACT11014 HEX SCHMITT-TRIGGER INVERTER SC A S 142A -03791. FEBRUARY 1991 -R E V IS E D APRIL1993 DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 54ACT11821, 74ACT11821 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS154A—D3715, NOVEMBER 1 9 9 0 - REVISED APRIL1993 54ACT11821 . . . JT PACKAGE 74ACT11821 . . . DW PACKAGE Inputs Are TTL-Voltage Compatible Provides Extra Data Width Necessary for

Contextual Info: 74ACT11273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SCAS130- D3443, MARCH 1990-R EV ISË D APRIL1993 DW OR NT PACKAGE TOP VIEW * Inputs Are TTL-Voltage Compatible * Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators * Flow-Through Architecture Optimizes

SRQ10

Contextual Info: 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER D3644. OCTOBER 1990-R EV ISE D APRIL1993 DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs 1 2 3 4 5 6 7 qf [ 8

fujitsu ten connector

Abstract: fujitsu ten lc ns73M SKS 25F CTS100 ht12 decoder
Contextual Info: M B 86965 FUJITSU ET H E R C O U P L E R SINGLE-CHIP E T H E R N E T CO N T R O L L E R APRIL1993 DATASHEET F E AT URE S • Provides interface to the I/O bus of PC/XT /AT or compatible computers • Optional, generic hostinterfaceto connect to industrystandard microprocessor buses

74ACT11657

Contextual Info: 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS _ Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout AUGUST 1992-REV1SED APRIL1993 DW PACKAGE TOP VIEW PARITY

k3525

Abstract: MBL8392A
Contextual Info: MBL8392A FUJITSU COAXIAL TRANSCEIVER INTERFACE FOR ETHERNET/THIN ETHERNET DATA SH EET APRIL1993 FEATURES During transmission the jabber timer is initiated to dis­ able the CTI transmitter in the event of a longer than legal length data packet. Collision detection circuitry

Contextual Info: 54ACT11520, 74ACT11520 8-BIT IDENTITY COMPARATORS SCAS009B —D2957, JULY 1987 - REVISED APRIL1993 Compares Two 8-Blt Words Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V^c and GND Configurations Minimize High-Speed Switching Noise

D3375

Contextual Info: 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE _ D3375, NOVEMBER 1989 - REVISED APRIL1993 * Flow-Through Architecture Optimizes PCB Layout * Center-PIn Vcc and GND Configurations Minimize High-Speed Switching Noise * EPIC"“ Enhanced-Performance Implanted

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987-R EVISED APRIL1993 I | * Compares Two 8-Bit Words • Flow-Through Architecture Optimizes PCB Layout 54AC11520. . . J PACKAGE 74AC11520. . . DW OR N PACKAGE TOP VIEW • Center-Pin V^c and GND Configurations

Contextual Info: 74ACT11802 TRIPLE 4-INPUT OR/NOR GATE SCAS153A- D3594, JULY 1990-R EV ISE D APRIL1993 DW OR NT PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin Vc c and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS S C A S Q 2 3 A - D2957, JU L Y 1978- R E V IS E D A P R I L 1993 54ACT11521 . . . J P A C K A G E 74ACT11521 . . . OB, D W O R N P A C K A G E i * Compares Two 8-Bit Words * Inputs Are TTL-Voltage Compatible

Contextual Info: 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR S C A S 1 7 8 - D 3 9 9 0 , D E C E M B E R 1991 - R E V IS E D A P R I L 1 9 9 3 Inputs Are TTL-Voltage Compatible Asynchronous Clear Fully Independent Clock Circuit Simplifies Use

d204d

Contextual Info: 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS101 - D3420, FEBRUARY 1990 - REVISED APRIL 1993 i * Contains Eight D-Type Flip-Flops * Clock Enable Latched to Avoid False Clocking DW OR NT PACKAGE TOP VIEW * Applications Include: Buffer/Storage Registers, Shift Registers, Pattern

CJJ 75W

Contextual Info: &• J S J s-iWAVjiai;^| au sws» * v, PÄ87 • PA87Ä AP EX M l C f t O T E C H N O L O G Y C O R P O R A T IO N ■T U C S O N . ARIZONA . A P P L I C A T I O N S HOT LIN E 8QO 5 4 6 - A P E X l PREUMINARY Product Introduction FEATURES * * * * HIGH VOLTAGE — 450V

MB86950 Etherstar Ethernet Controller

Abstract: MB86950 etherstar MB86962 MB86951 CODER MANCHESTER DIFFERENTIAL aui isolation transformer differential manchester encoder manchester encoder 10BASE2
Contextual Info: MB86951 CMOS ETHERNET ENCODER/DECODER DATA SHEET FEATURES • 10 Mbit/sec Manchester encoder/decoder • Compatible with IEEE 802.3 10BASE2, 10BASE5 and 10BASE-T specifications • Receiver clock recovery with dual phase locked loop for high stability • Decodes Manchester data with up to ±20 ns of jitter.

Contextual Info: 74AC11640 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS S C A S 052A -JU LY 1987 - REVISED A PR IL1993 I I | I ' * • • * * * Bidirectional Bus Transceivers in High-Density 24-Pin Packages Flow-Through Architecture Optimizes PCB Layout DW OR NT PACKAGE TOP VIEW

D2999

Contextual Info: SN65558, SN75558 ELECTROLUMINESCENT ROW DRIVERS SLDSD18B - D2999, DECEMBER 195 - REVISED APRIL 1993 • Each Device Drives 32 Electrodes FN PACKAGE {TOP VIEW N O t l O » K O O # O r <t V— T - 1 - 1 - 1 - Y - 1 - 1 - W O J O O O O O O O O O O O Z • High-Voltage Open-Collector NPN Outputs

Contextual Info: SAMSUNG ELECTRONICS INC b?E T> 7 *îb4 m s 0P17S1S bSO • SMGK PRELIMINARY BiCMOS SRAM KM68B261A ABSOLUTE MAXIMUM RATINGS* Item Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to VSs Power Dissipation Storage Temperature Operating Temperature

Contextual Info: 54ACT11138,74ACT11138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCAS050A - D3266, JANUARY 1989 - REVISED APRIL 1993 * Designed Specifically for High-Speed Memory Decoders and Data Transmission

74ACT11657

Contextual Info: 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS _ AUGUST 1992-R EV IS ED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Pin Configurations Minimize High-Speed

Contextual Info: 74AC11257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS _ D3259,MARCH 1989-REVISEDAPBIL1993 DW OR N PACKAGE TOP VIEW * 3-State Outputs Interface Directly With System Bus * Flow-Through Architecture Optimizes

MAA 723

Contextual Info: 74AC11153 DUAL 1-0F-4 DATA SELECTOR/MULTIPLEXER D 3582, JU N E 1990 - R EVISED A P R IL 1993 Permits Multiplexing From N Lines to 1 Line Performs Parallel-to-Serial Conversion □ OR N PACKAGE TOP VIEW A [ 1 B [ 2 Strobe (Enable) Line Provided for Cascading (N Lines to N Lines)

74AC11239

Contextual Info: 74AC11239 DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER S C A S 072A -JU LY 1 9 8 9 - REVISED A P R IL I 993 D OR N PACKAGE * Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems TOP VIEW * Incorporates Two Enable Inputs to Simplify