IL1993 Search Results
IL1993 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
|
Contextual Info: 74AC11640 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS S C A S 052A -JU LY 1987 - REVISED A PR IL1993 I I | I ' * • • * * * Bidirectional Bus Transceivers in High-Density 24-Pin Packages Flow-Through Architecture Optimizes PCB Layout DW OR NT PACKAGE TOP VIEW |
OCR Scan |
74ac11640il199324-pin500-ma+1 | |
ACT16244
Abstract: 74ACT16244 D3465
|
OCR Scan |
54act1624474act1624416-bitscas116a+7 | |
|
Contextual Info: 74AC11643 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS S C A S 057A -JU LY 1987 - REVISED A PR IL1993 I I | I ' * Bidirectional Bus Transceivers in High-Density 24-Pin Packages Flow-Through Architecture Optimizes PCB Layout • • DW OR NT PACKAGE TOP VIEW |
OCR Scan |
74ac11643il199324-pin500-ma+1 | |
|
Contextual Info: 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ SCAS115- D3456, MARCH 1990-REVISEDAPRIL 1933 Inputs Are TTL-Voltage Compatible Independent Registers A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths |
OCR Scan |
74act11648scas115-d34561990-revisedapril+1 | |
P34S8
Abstract: 74ACT11648
|
OCR Scan |
74act11648scas115p34s8500-ma+2 | |
|
Contextual Info: 54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS018A —D2957, JULY 1 9 8 7 -R E V IS E D A P R IL 1 9 9 3 54ACT11010. . . J PACKAGE 74ACT11010. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible * Flow-Through Architecture to Optimize PCB Layout |
OCR Scan |
54act1101074act11010scas018ad2957+2 | |
MB7B
Abstract: 74ACT16474
|
OCR Scan |
74act1647418-bit300-mil25-mil+3 | |
TLV2362
Abstract: TLV2362ID TLV2362IDR TLV2362IP TLV2362IPWLE TLV2362Y t994
|
OCR Scan |
tlv2362tlv2362yslos126a-100pf+5 | |
74ACT16241Contextual Info: 74ACT16241 16-BIT BUFFER DRIVER WITH 3-STATE OUTPUTS S C A S 1 8 9 -D 3 4 6 5 , M ARCH 1990 - REVISED APRIL 1993 Member of the Texas Instruments Widebus Family DL PACKAGE TOP VIEW Packaged in Plastic 300-mil Shrink Small-Outline Package Using 25-mil Center-to-Center Pin Spacings |
OCR Scan |
74act1624116-bitscas189-d3465300-mil+3 | |
|
Contextual Info: 54AC11112,74AC11112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ Flow-Through Architecture Optimizes PCB Layout D3334, JUNE 1 9 8 9 - REVISED APRIL 1993 54AC11112 . . . J PACKAGE 74AC11112 . . . D OR N PACKAGE |
OCR Scan |
54ac1111274ac11112d3334500-ma+3 | |
P3478
Abstract: 54ACT16646 74ACT16646
|
OCR Scan |
54act1664674act1664616-bitscas127a-d3478+6 |