MBL8392A Search Results

MBL8392A

Abstract: TRANSFORMER 9V 500 ma MBL8392 10BASE2 10BASE5 MBL8393APD-G MBL8393AP-G
Contextual Info: MBL8392A COAXIAL TRANSCEIVER INTERFACE FOR ETHERNET/THIN ETHERNET DATA SHEET FEATURES • Compatible with Ethernet II, IEEE 802.3 10BASE5 and 10BASE2, and ISO 8802/-3 interface specifications • Integrates all active transceiver electronics • Only one external resistor required for setting coaxial

k3525

Abstract: MBL8392A
Contextual Info: MBL8392A FUJITSU COAXIAL TRANSCEIVER INTERFACE FOR ETHERNET/THIN ETHERNET DATA SH EET APRIL1993 FEATURES During transmission the jabber timer is initiated to dis­ able the CTI transmitter in the event of a longer than legal length data packet. Collision detection circuitry

jrm a40

Abstract: U/25/20/TN26/15/850/tl-130 transformer
Contextual Info: MBL8392A FUJITSU COAXIAL TRANSCEIVER INTERFACE FOR ETHERNET/THIN ETHERNET DATASHEET APRILI 993 FEATURES Compatible with Ethernet n , IEEE 802.3 10BASE5 and 10BASE2, and ISO 8802/-3 interface specifica­ tions Integrates all active transceiver electronics Only one external resistor required for setting coaxial

MB86950 Etherstar Ethernet Controller

Abstract: MB86950 etherstar MB86962 MB86951 CODER MANCHESTER DIFFERENTIAL aui isolation transformer differential manchester encoder manchester encoder 10BASE2
Contextual Info: MB86951 CMOS ETHERNET ENCODER/DECODER DATA SHEET FEATURES • 10 Mbit/sec Manchester encoder/decoder • Compatible with IEEE 802.3 10BASE2, 10BASE5 and 10BASE-T specifications • Receiver clock recovery with dual phase locked loop for high stability • Decodes Manchester data with up to ±20 ns of jitter.

fujitsu ten connector

Abstract: fujitsu ten lc ns73M SKS 25F CTS100 ht12 decoder
Contextual Info: M B 86965 FUJITSU ET H E R C O U P L E R SINGLE-CHIP E T H E R N E T CO N T R O L L E R APRIL1993 DATASHEET F E AT URE S • Provides interface to the I/O bus of PC/XT /AT or compatible computers • Optional, generic hostinterfaceto connect to industrystandard microprocessor buses

Contextual Info: M B86960 F ilim i! NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATASHEET A P R IL I 9 9 3 FEA TU R ES • High-performance packet buffer architecture pipe­ lines data for highest throughput • 20 Mbyte/second datatransferrate to/from thesystem

Contextual Info: M B 8 6 9 6 5 A/M B 8 6 9 6 5 B FUJITSU ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATASHEET Note: All descriptions apply to both the M B86965A and MB86965B FEATURES • Provides interface to the I/O bus of PC/XT /AT or compatible computers • Optional, generic host interface to connect to industrystandard microprocessor buses

Contextual Info: MB86965 FUJITSU ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATASHEET APRILI 993 FEATURES Provides interface to the I/O bus of PC/XT /AT or compatible computers Optional, generic host interface to connect to industrystandard microprocessor buses Interface to serial EEPROM for Node ID and configu­

fujtsu

Abstract: RBS02 BUT16
Contextual Info: MB86960 FUJITSU NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATA SHEET A P R ILI 993 superior benchmark speed and application performance. The NICE device has a partitionable 2, 4, 8, or 16 kilobyte, two-bank, transmit buffer which allows multiple data packets to be “chained” together and trans­

MB86950 Etherstar Ethernet Controller

Abstract: MB86950 MBL8392A
Contextual Info: FEATURES DESCRIPTION • C om panion chip for M B 86950 EtherStar or M B86960 NICE™ Ethernet LAN controllers • Provides interface between controller and IBM PC, XT or AT bus • Substantially reduces parts count for LAN adapter • 8- and 16-bit bus capability

C2650N

Abstract: MB86950 L8392A
Contextual Info: MB86951 FUJITSU CMOS ETHERNET ENCODER/DECODER APRILI 993 DATA SHEET balanced differential pair to the transceiver. During receive operation it converts M anchester encoded data on a balanced differential pair from the transceiv­ er into N R Z data and forw ards it to the controller,

PM6501

Abstract: BMPR10 VALOR PM6501 10BASE2 10BASE5 MB86960 MB86961 MB86965 MB84256 150145
Contextual Info: MB86965 ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATA SHEET FEATURES • Provides interface to the I/O bus of PC/XT/AT or compatible computers • Optional, generic host interface to connect to industrystandard microprocessor buses • Interface to serial EEPROM for Node ID and configuration option storage allows construction of jumperless, electronically configurable adapter cards

PM6501

Abstract: PM6501 dc to dc VALOR PM6501 10BASE2 10BASE5 MB86960 MB86961 MB86965 MBL8392A BMPR10
Contextual Info: MB86965 ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATA SHEET FEATURES • Provides interface to the I/O bus of PC/XT/AT or compatible computers • Optional, generic host interface to connect to industrystandard microprocessor buses • Interface to serial EEPROM for Node ID and configuration option storage allows construction of jumperless, electronically configurable adapter cards

MB86953

Abstract: fault codes for RBS BD10 BD12 MB86960 BUT16
Contextual Info: MB86960 NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATA SHEET FEATURES • High-performance packet buffer architecture pipelines data for highest throughput • 20 Mbyte/second data transfer rate to/from the system bus • on-chip buffer controller manages pointers, reduces

Contextual Info: MB86951_ FUJITSU CMOS ETHERNET ENCODER/DECODER DATASHEET FEATURES • 10 Mbit/sec Manchester encoder/decoder • Compatible with IEEE 802.3 10BASE2,10BASE5 and 10BASE-T specifications • Receiver clock recovery with dual phase locked loop

Contextual Info: FUJITSU MB86960 NICE Ethernet Controller FACT SHEET JUNE 1990 DESCRIPTION FEATURES 20 Mbytes/second data transfer rate to the system bus On-chip Buffer Management Unit reduces software overhead High-speed burst and single transfer DMA Bus compatibility for all standard microprocessors

xmtd

Abstract: MB86965A 10BASE 10BASE2 10BASE5 MB86965 MB86965B LSA0 memory BMPR18
Contextual Info: MB86965A/MB86965B ETHERCOUPLER SINGLE-CHIP ETHERNET CONTROLLER DATA SHEET Note: All descriptions apply to both the MB86965A and MB86965B FEATURES • Provides interface to the I/O bus of PC/XT/AT or compatible computers • Optional, generic host interface to connect to industrystandard microprocessor buses

RPY 86

Abstract: BUT16
Contextual Info: M B 86960 FUJITSU N E T W O R K INTERFACE CO N T R O L L E R with E N C O D E R / D E C O D E R NICE DATASHEET FEATURES High-performance packet buffer architecture pipe­ lines data for highest throughput 20 Mbyte/second data transferrate to/from the system

Contextual Info: FUJITSU MB86951 CMOS Ethernet Encoder/Decoder FACT SHEET JUNE 1990 FEATURES DESCRIPTION • The CMOS M B86951 is a functionally complete Serial Network Interface SNI that provides the Manchester data encoding and decoding functions for Ethernet (10BASE5) and Thin Ethernet

MB502A

Abstract: datasheet HT12 D ht12 decoder MB86960APF-G mb86953 BD10 BD12 MB86960 BUT16
Contextual Info: MB86960 NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATA SHEET FEATURES • High-performance packet buffer architecture pipelines data for highest throughput • 20 Mbyte/second data transfer rate to/from the system bus • on-chip buffer controller manages pointers, reduces