AN1406 Search Results

AN1406

Abstract: DL140 transistor E111 signal path designer
Contextual Info: AN1406 Application Note Designing With PECL ECL at +5.0V Prepared by Cleon Petty Todd Pearson ECL Applications Engineering This application note provides detailed information on designing with Positive Emitter Coupled Logic (PECL) devices. 9/92  Motorola, Inc. 1996

Contextual Info: Chapter Eight Application Notes Application Notes Document Number Page AN1091/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 AN1405/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 AN1406/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

"USB mp3 player" circuit diagram

Abstract: USB connector DIAGRAM USB connector mp3 player circuit diagram jack J10 stereo usb music player usb to audio rca schematic headphone to rca schematic circuit usb mp3 player rca 036
Contextual Info: ISL54209EVAL1Z Evaluation Board User’s Manual Application Note Description July 14, 2008 AN1406.0 Picture of Evaluation Board Top View The ISL54209EVAL1Z evaluation board is designed to provide a quick and easy method for evaluating the ISL54209 USB/Audio Switch IC.

signal path designer

Contextual Info: Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: AN1406/D Rev 2, 08/2001 AN1406 Designing With PECL ECL at +5.0 V The High Speed Solution for the CMOS/TTL Designer Prepared by: Cleon Petty, Todd Pearson ECL Applications Engineering

AN1406

Abstract: MECL System Design Handbook DL140 signal path designer
Contextual Info: AN1406 Application Note Designing With PECL ECL at +5.0V Prepared by Cleon Petty Todd Pearson ECL Applications Engineering This application note provides detailed information on designing with Positive Emitter Coupled Logic (PECL) devices. 2/98  Motorola, Inc. 1998

HB205/d

Abstract: small signal transistor MOTOROLA DATABOOK cmos logic databook AN1406
Contextual Info: Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: AN1406/D Rev 2, 08/2001 Designing With PECL ECL at +5.0 V AN1406 The High Speed Solution for the CMOS/TTL Designer Prepared by: Cleon Petty, Todd Pearson ECL Applications Engineering

Contextual Info: Chapter Nine Application Notes Application Notes Document Number Page AN1091/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 AN1405/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 AN1406/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783

signal path designer

Abstract: DL140-D
Contextual Info: MOTOROLA Order Number: AN1406/D SEMICONDUCTOR TECHNICAL DATA Rev 2, 08/2001 AN1406 Designing With PECL ECL at +5.0 V The High Speed Solution for the CMOS/TTL Designer Prepared by: Cleon Petty, Todd Pearson ECL Applications Engineering ABSTRACT This application note provides detailed information on

signal path designer

Contextual Info: MOTOROLA Order Number: AN1406/D SEMICONDUCTOR TECHNICAL DATA Rev 2, 08/2001 AN1406 Designing With PECL ECL at +5.0 V The High Speed Solution for the CMOS/TTL Designer Prepared by: Cleon Petty, Todd Pearson ECL Applications Engineering ABSTRACT This application note provides detailed information on

AN1406

Abstract: MECL handbook noise specs confusing signal path designer
Contextual Info: AN1406/D Designing with PECL ECL at +5.0 V The High Speed Solution for the CMOS/TTL Designer http://onsemi.com Prepared by Cleon Petty Todd Pearson ECL Applications Engineering APPLICATION NOTE This application note provides detailed information on designing with Positive Emitter Coupled Logic (PECL) devices.

10H125

Abstract: signal path designer MC10125 application
Contextual Info: Freescale Semiconductor, Inc. Order number: AN1406 Rev 2, 08/2001 APPLICATION NOTE AN1406 Designing With PECL ECL at +5.0 V The High Speed Solution for the CMOS/TTL Designer By: Cleon Petty, Todd Pearson ECL Applications Engineering ABSTRACT This application note provides detailed information on designing with Positive Emitter Coupled Logic (PECL) devices.

Contextual Info: AN1406 Application Note Designing W ith PECL ECL a t +5.0V P repared b y Cleon Petty Todd Pearson ECL A pplications Engineering This application note p rovides d e tailed inform ation on designing with P ositive E m itter C oupled Logic (PECL) devices. TIMING SOLUTIONS

100EL91

Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
Contextual Info: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them

E212 transistor

Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
Contextual Info: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock

KPT25

Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
Contextual Info: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal

LQFP32

Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
Contextual Info: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs

marking CODE D2B

Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
Contextual Info: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be

KVT23

Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
Contextual Info: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which

MC100EP90

Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
Contextual Info: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.

MC100E116

Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
Contextual Info: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.

MC100LVEL01

Abstract: MC100LVEL01D 1085 SPICE model
Contextual Info: MC100LVEL01 3.3VĄECL 4-Input OR/NOR The MC100LVEL01 is a 4–input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in

KEL04

Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
Contextual Info: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those

N100

Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
Contextual Info: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.

KEP05

Abstract: HEP05 MC100EP05 MC10EP05
Contextual Info: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance