AD9513 Search Results

Contextual Info: 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs AD9513 FUNCTIONAL BLOCK DIAGRAM FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust Three 800 MHz/250 MHz LVDS/CMOS clock outputs

Contextual Info: Evaluation Board for AD9513/AD9514/ AD9515 Clock Distribution ICs AD9513/PCB, AD9514/PCB, AD9515/PCB be set to either LVDS or CMOS. The AD9515 offers two independent clock outputs, one as LVPECL, the other is selectable as either LVDS or CMOS levels. EVALUATION BOARD DESCRIPTION

AD9513

Abstract: AD9513 application note
Contextual Info: 9513_quick_start.clk Design Example Description a In this design the AD9513, 800MHz, 3-Channel Clock Distribution IC is used to provide clocks to three analogto-digital converters ADCs . All three ADCs require clocks with broadband jitter < 400 femtoseconds rms. All three ADCs require CMOS

Contextual Info: Preliminary Technical Data 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs AD9513 FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust 3 800 MHz/250 MHz LVDS/CMOS clock outputs

AD9513

Abstract: AN-501 AN-586 AN-756 ZESC-2-11 ZFL1000VH2 ANALOG DEVICES AD9513BCPZ 4069 CMOS filter
Contextual Info: 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs AD9513 FEATURES 1.6 GHz differential clock input 3 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust Three 800 MHz/250 MHz LVDS/CMOS clock outputs

LC1210

Abstract: PIC H501 OSC500 ic c575 diagram SMDC110F K3638 SMDC110F-2 adc c520 cd 1691 cp cp c531
Contextual Info: 12位, 80 MSPS/105 MSPS/125 MSPS, 18V模数转换器 AD9233 功能框图 特性 应用 超声设备 中频采样的通信接收机 IS-95CDMA-One、IMT-2000 电池供电仪表 手持式示波仪 低成本数字示波器 概述 AD9233是一款单芯片、12位、80 MSPS/ 105 MSPS/125 MSPS

max9291

Abstract: AD6643-200 CP-64-4 901MH AN83-5 10-com 1401M 10True
Contextual Info: Dual IF Receiver AD6643 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0±

17D06

Abstract: 16D06 D01N
Contextual Info: FEATURES APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Handheld scope meters

E19 CORE TRANSFORMER

Abstract: CP-48-1 AD9524
Contextual Info: 80 MHz Bandwidth, Dual IF Receiver AD6673 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD DVDD AGND DGND DRGND AD6673 VIN+A VIN–A PIPELINE 11-BIT ADC JESD-204B INTERFACE NSR VCM VIN+B VIN–B SYSREF± SYNCINB± CLK± RFCLK PIPELINE 11-BIT ADC HIGH

AD9250

Abstract: E19 CORE TRANSFORMER AD9524 upstream docsis cmts JESD204B
Contextual Info: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter AD9250 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD AGND DGND DRGND AD9250 VIN+A VIN–A PIPELINE 14-BIT ADC VCM VIN+B VIN–B PIPELINE 14-BIT ADC JESD-204B INTERFACE SERDOUT0± CML, TX

956d

Abstract: AD9258 D15A AD9269-40EBZ 765D
Contextual Info: 16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9269 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation 1.8 V to 3.3 V output supply Integrated quadrature error correction QEC SNR 77.6 dBFS at 9.7 MHz input 71 dBFS at 200 MHz input

max8895

Abstract: AD9613BCPZ-250
Contextual Info: FEATURES SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS SFDR = 86 dBc at 185 MHz fIN and 250 MSPS −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 770 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs

AD9467

Abstract: B0205F5050A00 AD520* differential amplifier
Contextual Info: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter AD9467 Data Sheet 75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS 92 dBFS at −1 dBFS 100 dBFS at −2 dBFS 60 fs rms jitter Excellent linearity at 250 MSPS

circuit diagram of analog clock using logic gates

Contextual Info: FEATURES SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 785 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs

smd diode c644

Abstract: diode c649 smd diode c548 C748 SMC transistor C734 smd diode c549 C706 diode c624 DIODE smd diode C645 diode c741
Contextual Info: Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter AD9222 8 ADCs integrated into 1 package 93 mW ADC power per channel at 50 MSPS SNR = 70 dB to Nyquist ENOB = 11.3 bits SFDR = 84 dBc Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical)

an-877application

Contextual Info: 16-Bit, 125 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9268 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 78.2 dBFS @ 70 MHz SFDR = 88 dBc @ 70 MHz Low power: 750 mW @ 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply Integer 1-to-8 input clock divider

center tap transformer 18 0 18

Abstract: C532 diode 6562D 9018D
Contextual Info: Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter AD9259 4 ADCs integrated into 1 package 98 mW ADC power per channel at 50 MSPS SNR = 73 dB to Nyquist ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.5 LSB (typical) INL = ±1.5 LSB (typical)

AD9258BCPZ-125

Abstract: AD9258-105 AD9258 850dBc AD9258-125
Contextual Info: 14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9258 FEATURES APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems

ad9649 evaluation

Abstract: 957D smart antenna AD9649-40EBZ CSB350
Contextual Info: FEATURES APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR

AD951x

Contextual Info: Quad IF Receiver AD6657A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD DRGND AD6657A VIN+A PIPELINE ADC VIN–A 14 NOISE SHAPING REQUANTIZER DO±AB VCMA VIN+B PIPELINE ADC VIN–B 14 NOISE SHAPING REQUANTIZER 11 VCMB VIN+C PIPELINE ADC VIN–C

Contextual Info: 16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9269 Preliminary Technical Data FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 77 dBFS at 10 MHz input 73 dBFS at 170 MHz input SFDR 90 dBc at 10 MHz input

HSM2822

Abstract: pra 1122
Contextual Info: 8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter ADC AD9286 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Single 1.8 V supply operation SNR: 48.3 dB to 200 MHz input at 500 MSPS SFDR: 65 dBc to 200 MHz input at 500 MSPS Low power: 310 mW at 500 MSPS

c606 Schottky diode

Abstract: avago bar code on the box smd diode c644
Contextual Info: Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC AD9252 8 analog-to-digital converters ADCs integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical)

AD9268BCPZ-125

Contextual Info: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9268 Preliminary Technical Data FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 77.3 dBc 78.3 dBFS to 70 MHz @ 125 MSPS SFDR = 88 dBc to 70 MHz @ 125 MSPS (w/o dither) Low power: 675 mW @ 125 MSPS