AC377 Search Results

Contextual Info: AC377 • ACT377 54AC/AC377 • 54ACT/74ACT377 Octal D Flip-Flop With Clock Enable Connection Diagrams Description The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all

54AC377

Abstract: 54AC377DMQB 54AC377FMQB 54AC377LMQB AC377
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 07/01/96 Last Update Date: 03/31/97 Last Major Revision Date: 07/01/96 AC377-X REV 1B0 Octal D-Type Flip - Flop With Clock Enable General Description The AC377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q

AC377

Abstract: ACT377 54ACT 74AC
Contextual Info: AC377 • ACT377 54AC/AC377 • 54ACT/74ACT377 Octal D Flip-Flop W ith Clock Enable Connection Diagrams Description The ’AC/’AC T 3 7 7 h a s eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The com m on buffered C lo c k CP input loads all

Contextual Info: AC377 • ACT377 54AC/AC377 • 54ACT/74ACT377 Octal D Flip-Flop With Clock Enable Description Connection Diagrams The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all

Contextual Info: AC377 • ACT377 54AC/AC377 • 54ACT/74ACT377 Octal D Flip-Flop W ith Clock Enable Description Connection Diagrams The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all

specifications of transistor AC126

Abstract: hc132a hc138a specifications of AC126 HC74A TC7PGU04FU transistor AC126 hc273a -toshiba toshiba vhc32 TC4W53FU
Contextual Info: SEMICONDUCTOR GENERAL CATALOG General-Purpose Logic ICs CMOS Logic ICs Low-Voltage CMOS Logic ICs CMOS Logic ICs in Ultra-Small US Packages Dual-Supply Level Shifters CMOS Bus Switch ICs Application-Specific Logic One-Gate CMOS L-MOS 1 2009-8 SCE0004I CMOS Logic ICs (74AC, 74VHC, 74HC and Standard Series) Quick Reference

74 Series Logic ICs

Abstract: transistor AC126 74HC octal bidirectional latch cx 4060 8pin hc257a TC7PG17AFE TC7SG07FE Transistor 123AP AC139 hc11a
Contextual Info: General-Purpose Logic ICs CMOS Logic ICs z 94 Low-Voltage CMOS Logic ICs z 100 CMOS Logic ICs in Ultra-Small US Packages z 104 Dual-Supply Level Shifters z 106 CMOS Bus Switch ICs z 108 Application-Specific Logic z 110 One-Gate CMOS L-MOS z 112 89 CMOS Logic ICs (74AC, 74VHC, 74HC and Standard Series) Quick Reference

transistor AC126

Abstract: equivalent transistor ac125 AC393 AC126 74AC393 AC365 AC682 d flip flop p6nk60z ACT03
Contextual Info: HC Portfolio Comparison PART # AC00 ACT00 AC01 AC02 ACT02 AC03 ACT03 AC04 ACT04 ACU04 AC05 ACT05 AC07 AC08 ACT08 AC09 AC10 ACT10 AC11 ACT11 AC14 ACT14 AC20 ACT20 AC32 ACT32 AC74 ACT74 AC86 ACT86 AC107 AC109 ACT109 AC112 ACT112 AC123 AC125 ACT125 AC126 ACT126

E27014

Contextual Info: AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable General Description The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.

TU 55x

Abstract: tl 4216 AC377 SD1122
Contextual Info: NATIONAL SEf1IC0N]> LOGIC blE D • fcjSD1122 DDVMTSl IMI M N S C l T" S 3 N a tio n a l ÆlM Semiconductor 54AC/AC377 • 54ACT/74ACT377 Octal D Flip-Flop with Clock Enable General Description Features The ’A C /’ACT377 has eight edge-triggered, D-type flip-flops

Contextual Info: 5 4 A C /7 4 A C 3 7 7 • 54 A C T /7 4 A C T 3 7 7 O ctal D Flip-Flop w ith Clock Enable General Description Features The ’A C /’AC T377 has eight edge-triggered, D -type flip-flo p s w ith individual D inputs and Q outputs. The com m on b u ff­ ered C lock CP input loads all flip-flo p s sim ultaneously,

MC74AC273

Abstract: MC74AC373
Contextual Info: AC377, MC74ACT377 Octal D Flip−Flop with Clock Enable The AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered.

VHCV541

Abstract: VHC9164 TC7PZ17FU TC7WZ07FK HCT688A VHCV17 TC7LX1108 14 pin ic 4027 TC 9164 N VHCV244
Contextual Info: 東芝半導体製品総覧表 2011 年 1 月版 汎用ロジック IC CMOS ロジック IC CMOS ロジック IC 低電圧 CMOS ロジック IC (超小型 US パッケージ) 2 電源レベルシフタ CMOS バススイッチ IC 特定用途向けロジック

54ACT

Abstract: 74AC 74AC377 74ACT377 AC377 C1995 74ACT377 national
Contextual Info: 54AC AC377  54ACT 74ACT377 Octal D Flip-Flop with Clock Enable General Description Features The ’AC ’ACT377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock CP input loads all flip-flops simultaneously

54ACT

Abstract: 74AC AC377
Contextual Info: March 1993 54A C /7 AC377 • 54ACT/74ACT377 Octal D Flip-Flop with Clock Enable General Description Features The ’A C /’AC T377 has eight edge-triggered, D -type flip-flops w ith individual D inputs and Q outputs. The com m on b u ff­ ered C lock CP input loads all flip-flo p s sim ultaneously,

AC377

Abstract: MC74AC273 MC74AC373 MC74ACT377DWR2 MC74AC374 MC74AC377 MC74ACT377
Contextual Info: AC377, MC74ACT377 Octal D Flip−Flop with Clock Enable The AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered.

LCX16244

Abstract: "Inverter Gates" HCT245A hc74a 14 pin ic 4027 hc08a AC126 CMOS 4584 HC138A hc157a
Contextual Info: 東芝半導体製品総覧表 2009 年 7 月版 汎用ロジック IC CMOS ロジック IC CMOS ロジック IC 低電圧 CMOS ロジック IC (超小型 US パッケージ) 2 電源レベルシフタ CMOS バススイッチ IC 特定用途向けロジック

54ACT

Abstract: 74AC AC377
Contextual Info: March 1993 54A C /7 AC377 • 54ACT/74ACT377 Octal D Flip-Flop with Clock Enable General Description Features The ’A C /’AC T377 has eight edge-triggered, D -type flip-flops w ith individual D inputs and Q outputs. The com m on b u ff­ ered C lock CP input loads all flip-flo p s sim ultaneously,

L3257C

Abstract: vhc9541 VHCT9273 TC7LX1102 VHC9273 vhc*t08a TC7LX1104 vhc165 L3125C VCXHR162245
Contextual Info: 東芝半導体製品総覧表 2010 年 1 月版 汎用ロジック IC CMOS ロジック IC CMOS ロジック IC 低電圧 CMOS ロジック IC (超小型 US パッケージ) 2 電源レベルシフタ CMOS バススイッチ IC 特定用途向けロジック

specifications of transistor AC126

Abstract: 74 Series Logic ICs gate diagrams octal Bilateral Switches specifications of AC126 TC4000 series CMOS Logic ICs inverter TC74HC(T)XXXAP 74HC octal bidirectional latch specifications transistor AC126 VHCV541 TC7PZ17FU
Contextual Info: SEMICONDUCTOR GENERAL CATALOG General-Purpose Logic ICs CMOS Logic ICs Low-Voltage CMOS Logic ICs CMOS Logic ICs in Ultra-Small US Packages Dual-Supply Level Shifters CMOS Bus Switch ICs Application-Specific Logic One-Gate CMOS L-MOS 1 2010/9 SCE0004K

land pattern ssop8

Abstract: TC4000 series CMOS Logic ICs st lcx125 HC 4011 logic gate HC74A TC7LX1108WBG cmos ic cd 4066 Quad Analog Switch TC7SZ34FU st lcx32 4013 FLIP FLOP APPLICATION DIAGRAMS
Contextual Info: 2010-9 PRODUCT GUIDE General-Purpose Logic ICs h t t p : / / w w w. s e m i c o n . t o s h i b a . c o . j p / e n g ▲ ▲ ▲ ▲ ▲ Toshiba General-Purpose Logic Family . Family Positioning: Supply Voltages vs Speeds .

MC74AC273

Abstract: MC74AC373 MC74ACT377DWR2 MC74AC374 MC74AC377 MC74ACT377
Contextual Info: AC377, MC74ACT377 Octal D Flip−Flop with Clock Enable The AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered.

Contextual Info: General Description Ideal for addressable register applications Clock enable for address and data synchronization applications Eight edge-triggered D flip-flops Buffered common clock Outputs source/sink 24 mA See ’273 for master reset version See ’373 for transparent latch version

54AC377

Abstract: 54ACT377 AC377
Contextual Info: AC377 • 54ACT377 Octal D Flip-Flop with Clock Enable General Description The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.