8TO32 Search Results

vsc710

Contextual Info: PRELIMINARY DATA SHEET 7/1/92 G-TAXIchips VITESSE TM VSC7101/VSC7102/VSC7103/VSC7104 SEMICONDUCTOR CORPORATION 1.25 Gbits/sec Data Communications Chipset G-TAXIchip Features General Description • Compatible with ANSI X3T9.3 Fiber Channel Standard The G-TAXIchips are a general purpose inter­

80960CA

Abstract: RT-1112 CX 879 128 bit processor schematic 80960CF i960 Cx Processor Instruction Set Quick Reference A-18 solutions960 catalog TTL catalog i960 Cx Processor
Contextual Info: i960 CA/CF Microprocessor User’s Manual March 1994 Order Number: 270710-003 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.

ADSP21161

Abstract: ADSP-21161 EE-150 EE-151 EE-66
Contextual Info: Engineer To Engineer Note EE-151 Technical Notes on using Analog Devices’ DSP components and development tools Phone: 800 ANALOG-D, FAX: (781) 461-3010, EMAIL: dsp.support@analog.com, FTP: ftp.analog.com, WEB: www.analog.com/dsp Copyright 2002, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for

XC2V1000FG256-4

Abstract: XAPP639 XC2V1000 XC2V3000 flood v10 crc verilog code 16 bit XC2V1000-FG256
Contextual Info: Application Note: Virtex-II Family R HyperTransport Lite Interface for Virtex-II FPGAs XAPP639 v1.0 January 7, 2003 Summary HyperTransport is a high-speed bus designed to move data from processors to peripherals at speeds up to 60 times faster than a 32-bit PCI bus operating at 66 MHz. The HyperTransport

VL16C450

Abstract: VL86C410 VL86C410-08QC
Contextual Info: L S I TECHNOLOGY INC Tfl ^300347 ODOlbSl M V L S I Technology, inc . T"~73- 31-¿?7 VL86C410 RISC I/O CONTROLLER IOC FEATURES DESCRIPTION • Power on reset control The VL86C410 Input/Output Controller (IOC) is designed to Interface fo the VL86C010/VL86C110/VL86C310 chip

K9F1208* technical

Abstract: Flash Memory SAMSUNG "NAND Flash" nand flash toshiba Nand flash ADSP-21262 EE-279 K9F1208R0B K9F1208U0B K9F1208x0B
Contextual Info: Engineer-to-Engineer Note a EE-279 Technical notes on using Analog Devices DSPs, processors and development tools Visit our Web resources http://www.analog.com/ee-notes and http://www.analog.com/processors or e-mail processor.support@analog.com or processor.tools.support@analog.com for technical support.

222stm

Abstract: transistor fn 1016 ARM10 CODE16
Contextual Info: RealView Compilation Tools Version 2.0 Assembler Guide Copyright 2002, 2003 ARM Limited. All rights reserved. ARM DUI 0204C RealView Compilation Tools Assembler Guide Copyright © 2002, 2003 ARM Limited. All rights reserved. Release Information The following changes have been made to this book.

pSOS

Abstract: 460016 8572a 79S381 79S465 R3000 R3051 R3052 R3081 R36100
Contextual Info: Real-Time Operating Systems Integrated Systems, Inc. pSOSystem/MIPS Accelerated Technology, Inc. Software Development Tools Embedded Development for MIPS Processors Standard Features Description pSOSystem/MIPS provides a complete embedded application cross-development environment for the MIPS

pSOS

Abstract: 8572a MIPs datasheet 460016 79S381 VDIP Package 16C550 R4400 R4650 R4700
Contextual Info: Evaluation Boards Prometheus 4600 Integrated Real-Time Systems Preview Bulletin Standard Features ❏ MIPS R4400/4600/4650/4700 64-bit processors ❏ 150/100 MHz operation ❏ High speed FIFO interface ❏ Real-time clock ❏ High performance serial ports

crc verilog code 16 bit

Abstract: XC2V1000-FG256 00ff0000 hypertransport XAPP639 XC2V1000 XC2V3000 XC2V1000FG256-4 CLK-100 XC2V1000FG256-6
Contextual Info: Application Note: Virtex-II Family R HyperTransport Lite Interface for Virtex-II FPGAs XAPP639 v1.0.1 March 31, 2004 Summary HyperTransport is a high-speed bus designed to move data from processors to peripherals at speeds up to 60 times faster than a 32-bit PCI bus operating at 66 MHz. The HyperTransport

Contextual Info: VITESSE G-TAXIchips VSC7101 /V5C7 702/VSC7103/VSC7 704 1.25 Gbits/sec Data Communications Chipset G-TAXICHIP FEATURES • Compatible with ANSI X3T9.3 Fiber Channel Standard • Up to 1.25 Gbits/sec serial data rate • 32 or 40-bit wide parallel TTL data bus input